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1. 发明申请

US20090134525A1 Semiconductor device having a filling pattern around a storage structure and method of forming the same 失效
标题翻译：具有围绕存储结构的填充图案的半导体器件及其形成方法
公开(公告)号：US20090134525A1
公开(公告)日：2009-05-28
申请号：US12292673
申请日：2008-11-24
申请人： Jong-Wan Ma , Joon-Mo Kwon
发明人： Jong-Wan Ma , Joon-Mo Kwon
IPC分类号： H01L23/528
CPC分类号： H01L21/76844 , H01L21/76804 , H01L21/76831 , H01L21/76885 , H01L27/10817 , H01L27/10855 , H01L28/90
摘要： A semiconductor device includes an interlayer insulating layer on a semiconductor substrate, at least one plug on the semiconductor substrate, the plug extending through the interlayer insulating layer toward an upper portion of the semiconductor substrate, the plug having a lower part with a first diameter and an upper part with a second diameter different from the first diameter, a filling pattern on the interlayer insulating layer, the filling pattern surrounding the upper part of the plug, and an upper surface of the filling pattern being substantially coplanar with an upper surface of the plug, the upper surface of the plug facing away from the semiconductor substrate, and a protection pattern on the upper part of the plug, the protection pattern being between the plug, the filling pattern, and the interlayer insulating layer.
摘要翻译：半导体器件包括在半导体衬底上的层间绝缘层，半导体衬底上的至少一个插头，插头延伸穿过层间绝缘层朝向半导体衬底的上部，插头具有第一直径的下部，具有不同于第一直径的第二直径的上部，层间绝缘层上的填充图案，围绕插塞的上部的填充图案，以及填充图案的上表面基本上与插头，插头的上表面背离半导体衬底，以及在插头的上部上的保护图案，保护图案位于插头，填充图案和层间绝缘层之间。

2. 发明授权

US07148116B2 Semiconductor device with load resistor and fabrication method 失效
公开(公告)号：US07148116B2
公开(公告)日：2006-12-12
申请号：US11169894
申请日：2005-06-30
申请人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
发明人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
IPC分类号： H01L29/76
CPC分类号： H01L28/20 , H01L27/0802
摘要： A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.

3. 发明申请

US20060255391A1 METHOD OF FORMING A RELIABLE HIGH PERFORMANCE CAPACITOR USING AN ISOTROPIC ETCHING PROCESS 审中-公开
标题翻译：使用等压蚀刻工艺形成可靠的高性能电容器的方法
公开(公告)号：US20060255391A1
公开(公告)日：2006-11-16
申请号：US11459595
申请日：2006-07-24
申请人： Seung-Beom KIM , Won-Mo PARK , Yun-Jae LEE , Joon-Mo KWON , Myoung-Hee HAN , Man-Jong YU
发明人： Seung-Beom KIM , Won-Mo PARK , Yun-Jae LEE , Joon-Mo KWON , Myoung-Hee HAN , Man-Jong YU
IPC分类号： H01L29/00 , H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.
摘要翻译：本文公开了一种使用各向同性蚀刻工艺形成可靠的高性能电容器的方法，以优化下电极的表面积同时防止在下电极之间形成电桥。该方法包括在衬底上形成的多个牺牲氧化物层，具有接触插塞的绝缘层和蚀刻停止层。将牺牲氧化物层图案化并另外进行各向同性蚀刻以形成扩大的电容器孔。然后蚀刻停止层的暴露部分以形成露出接触插塞的上部和与其相邻的绝缘层的一部分的最终电容器孔。清洁具有最终电容器孔的半导体衬底以去除接触插塞的暴露的上部上的自然氧化膜。

4. 发明申请

US20060068539A1 Method of fabricating CMOS type semiconductor device having dual gates 失效
标题翻译：制造具有双栅极的CMOS型半导体器件的方法
公开(公告)号：US20060068539A1
公开(公告)日：2006-03-30
申请号：US11225914
申请日：2005-09-13
申请人： Byung-Jun Park , Joon-Mo Kwon
发明人： Byung-Jun Park , Joon-Mo Kwon
IPC分类号： H01L21/8238 , H01L21/31
CPC分类号： H01L21/823835 , H01L21/823842
摘要： According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well. P-type impurity ions are implanted into the N-type well, using the second ion implantation mask pattern as an ion implantation mask, to form second source and drain regions on both sides of the second gate electrode.
摘要翻译：根据一些实施例，提供制造具有双栅极的互补金属氧化物半导体（CMOS）型半导体器件的方法。该方法包括在P型阱上形成绝缘的第一栅电极，在N型阱上形成绝缘的第二初始栅电极。在P型阱上形成暴露第一栅电极的顶表面的第一下层间绝缘层，而在N型阱上形成暴露第二初始栅电极的顶表面的第二下层间绝缘层。选择性地将P型杂质离子注入第二初始栅电极以形成第二栅电极。在第一栅极上形成第一离子注入掩模图案，同时在第二栅电极上形成第二离子注入掩模图案。使用第二离子注入掩模图案作为蚀刻掩模蚀刻第二下层间绝缘层，以暴露N型阱的顶表面。使用第二离子注入掩模图案作为离子注入掩模将P型杂质离子注入到N型阱中，以在第二栅电极的两侧形成第二源区和漏区。

5. 发明申请

US20050255662A1 Semiconductor device with load resistor and fabrication method 失效
标题翻译：具有负载电阻的半导体器件及制造方法
公开(公告)号：US20050255662A1
公开(公告)日：2005-11-17
申请号：US11169894
申请日：2005-06-30
申请人： Won Lee , Joon-Mo Kwon , Tae Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
发明人： Won Lee , Joon-Mo Kwon , Tae Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
IPC分类号： H01L23/52 , H01L21/02 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/08 , H01L27/108 , H02H3/00 , H01L21/20 , H01L21/44 , H02H7/00
CPC分类号： H01L28/20 , H01L27/0802
摘要： A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
摘要翻译：制造具有负载电阻器的半导体器件，使得在负载电阻器的两端形成接触，并且在触点之间形成至少一个触点，以便防止在触点期间在每个触点内产生杂质通过蚀刻绝缘层产生的电荷产生，当蚀刻工艺制造绝缘层以在位于绝缘层下方的长负载电阻器中产生接触并在电和物理上绝缘时产生电荷现象。

6. 发明授权

US07192822B2 Method of fabricating CMOS type semiconductor device having dual gates 失效
标题翻译：制造具有双栅极的CMOS型半导体器件的方法
公开(公告)号：US07192822B2
公开(公告)日：2007-03-20
申请号：US11225914
申请日：2005-09-13
申请人： Byung-Jun Park , Joon-Mo Kwon
发明人： Byung-Jun Park , Joon-Mo Kwon
IPC分类号： H01L21/336
CPC分类号： H01L21/823835 , H01L21/823842
摘要： According to some embodiments, methods of fabricating a complementary metal oxide semiconductor (CMOS) type semiconductor device having dual gates are provided. The method includes forming an insulated first gate electrode on the P-type well, and an insulated second initial gate electrode on the N-type well. A first lower interlayer insulating layer exposing a top surface of the first gate electrode is formed on the P-type well while a second lower interlayer insulating layer exposing a top surface of the second initial gate electrode is formed on the N-type well. P-type impurity ions are selectively implanted into the second initial gate electrode to form a second gate electrode. A first ion implantation mask pattern is formed over the first gate electrode while a second ion implantation mask pattern is formed over the second gate electrode. The second lower interlayer insulating layer is etched, using the second ion implantation mask pattern as an etch mask, to expose a top surface of the N-type well. P-type impurity ions are implanted into the N-type well, using the second ion implantation mask pattern as an ion implantation mask, to form second source and drain regions on both sides of the second gate electrode.
摘要翻译：根据一些实施例，提供制造具有双栅极的互补金属氧化物半导体（CMOS）型半导体器件的方法。该方法包括在P型阱上形成绝缘的第一栅电极，在N型阱上形成绝缘的第二初始栅电极。在P型阱上形成暴露第一栅电极的顶表面的第一下层间绝缘层，而在N型阱上形成暴露第二初始栅电极的顶表面的第二下层间绝缘层。选择性地将P型杂质离子注入第二初始栅电极以形成第二栅电极。在第一栅极上形成第一离子注入掩模图案，同时在第二栅电极上形成第二离子注入掩模图案。使用第二离子注入掩模图案作为蚀刻掩模蚀刻第二下层间绝缘层，以暴露N型阱的顶表面。使用第二离子注入掩模图案作为离子注入掩模将P型杂质离子注入到N型阱中，以在第二栅电极的两侧形成第二源区和漏区。

7. 发明授权

US07825496B2 Semiconductor device having a filling pattern around a storage structure and method of forming the same 失效
标题翻译：具有围绕存储结构的填充图案的半导体器件及其形成方法
公开(公告)号：US07825496B2
公开(公告)日：2010-11-02
申请号：US12292673
申请日：2008-11-24
申请人： Jong-Wan Ma , Joon-Mo Kwon
发明人： Jong-Wan Ma , Joon-Mo Kwon
IPC分类号： H01L29/06
CPC分类号： H01L21/76844 , H01L21/76804 , H01L21/76831 , H01L21/76885 , H01L27/10817 , H01L27/10855 , H01L28/90
摘要： A semiconductor device includes an interlayer insulating layer on a semiconductor substrate, at least one plug on the semiconductor substrate, the plug extending through the interlayer insulating layer toward an upper portion of the semiconductor substrate, the plug having a lower part with a first diameter and an upper part with a second diameter different from the first diameter, a filling pattern on the interlayer insulating layer, the filling pattern surrounding the upper part of the plug, and an upper surface of the filling pattern being substantially coplanar with an upper surface of the plug, the upper surface of the plug facing away from the semiconductor substrate, and a protection pattern on the upper part of the plug, the protection pattern being between the plug, the filling pattern, and the interlayer insulating layer.
摘要翻译：半导体器件包括在半导体衬底上的层间绝缘层，半导体衬底上的至少一个插头，插头延伸穿过层间绝缘层朝向半导体衬底的上部，插头具有第一直径的下部，具有不同于第一直径的第二直径的上部，层间绝缘层上的填充图案，围绕插塞的上部的填充图案，以及填充图案的上表面基本上与插头，插头的上表面背离半导体衬底，以及在插头的上部上的保护图案，保护图案位于插头，填充图案和层间绝缘层之间。

8. 发明授权

US07101769B2 Method of forming a reliable high performance capacitor using an isotropic etching process 有权
标题翻译：使用各向同性蚀刻工艺形成可靠的高性能电容器的方法
公开(公告)号：US07101769B2
公开(公告)日：2006-09-05
申请号：US10776546
申请日：2004-02-10
申请人： Seung-Beom Kim , Won-Mo Park , Yun-Jae Lee , Joon-Mo Kwon , Myoung-Hee Han , Man-Jong Yu
发明人： Seung-Beom Kim , Won-Mo Park , Yun-Jae Lee , Joon-Mo Kwon , Myoung-Hee Han , Man-Jong Yu
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.
摘要翻译：本文公开了一种使用各向同性蚀刻工艺形成可靠的高性能电容器的方法，以优化下电极的表面积，同时防止在下电极之间形成电桥。该方法包括在衬底上形成的多个牺牲氧化物层，具有接触插塞的绝缘层和蚀刻停止层。将牺牲氧化物层图案化并另外进行各向同性蚀刻以形成扩大的电容器孔。然后蚀刻停止层的暴露部分以形成露出接触插塞的上部和与其相邻的绝缘层的一部分的最终电容器孔。清洁具有最终电容器孔的半导体衬底以去除接触插塞的暴露的上部上的自然氧化膜。

9. 发明授权

US07084478B2 Load resistor with dummy contact substantially free of charge build up during etching process 有权
标题翻译：在蚀刻过程中负载电阻器具有基本上不含电荷的虚拟接触
公开(公告)号：US07084478B2
公开(公告)日：2006-08-01
申请号：US10270563
申请日：2002-10-16
申请人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
发明人： Won Shik Lee , Joon-Mo Kwon , Tae Kyung Kim , Jin-Kee Choi , Dong-Gun Park , Hyeong-Chan Ko , Hong-Joon Moon
IPC分类号： H01L29/00
CPC分类号： H01L28/20 , H01L27/0802
摘要： A semiconductor device with a load resistor is manufactured such that a contact is formed at both ends of the load resistor, and at least one contact is formed between the contacts, in order to prevent impurities from being generated within each contact while the contacts are being generated by etching an insulation layer phenomena of electric charge build up from occurring when an etching process fabricates an insulation layer to generate the contact in a long load resistor located under the insulation layer and insulated electrically and physically.
摘要翻译：制造具有负载电阻器的半导体器件，使得在负载电阻器的两端形成接触，并且在触点之间形成至少一个触点，以便防止在触点期间在每个触点内产生杂质通过蚀刻绝缘层产生的电荷产生，当蚀刻工艺制造绝缘层以在位于绝缘层下方的长负载电阻器中产生接触并在电和物理上绝缘时产生电荷现象。

10. 发明申请

US20050218448A1 Transistor structure having an oxidation inhibition layer and method of forming the same 审中-公开
标题翻译：具有氧化抑制层的晶体管结构及其形成方法
公开(公告)号：US20050218448A1
公开(公告)日：2005-10-06
申请号：US11083457
申请日：2005-03-18
申请人： Dae-Ik Kim , Joon-Mo Kwon , Byung-Hak Lee
发明人： Dae-Ik Kim , Joon-Mo Kwon , Byung-Hak Lee
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8234 , H01L27/108
CPC分类号： H01L21/823456 , H01L21/823425 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A transistor structure and a method of forming the same prevent a boundary face of first and second gate electrodes from being oxidized in a subsequent oxidation process, by forming an oxidation inhibition layer in the boundary face. A gate insulation layer is formed on a semiconductor substrate, and a gate stack is obtained by a sequential accumulation of first and second gate electrodes and a capping layer on the gate insulation layer. An oxidation inhibition layer is formed in a sidewall portion of the gate stack, and the oxidation inhibition layer covers a boundary face of the first and second gate electrodes. Source/drain regions are opposite to the gate stack.
摘要翻译：晶体管结构及其形成方法通过在边界面中形成氧化抑制层，防止第一和第二栅极的边界面在随后的氧化过程中被氧化。在半导体衬底上形成栅极绝缘层，并且通过栅极绝缘层上的第一和第二栅电极和覆盖层的顺序堆积来获得栅叠层。在栅极堆叠的侧壁部分形成氧化抑制层，氧化抑制层覆盖第一和第二栅电极的边界面。源极/漏极区域与栅极堆叠相反。

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