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1. 发明申请

US20120035331A1 POLYALKYLTHIOPHENE BLOCK COPOLYMER AND A METHOD OF PREPARING THE SAME THROUGH A RING-OPENING METATHESIS POLYMERIZATION REACTION 审中-公开
标题翻译：聚烯烃嵌段共聚物及其通过开环元素聚合反应制备相同方法
公开(公告)号：US20120035331A1
公开(公告)日：2012-02-09
申请号：US13265258
申请日：2010-04-28
申请人： Hyun-ji Kim , Yun-Jae Lee , Kie-Yong Cho , Soon-Man Hong , Seung-Sang Hwang , Jyung-Youl Baek
发明人： Hyun-ji Kim , Yun-Jae Lee , Kie-Yong Cho , Soon-Man Hong , Seung-Sang Hwang , Jyung-Youl Baek
IPC分类号： C08G75/06
CPC分类号： C08G61/126 , C08G2261/126 , C08G2261/1642 , C08G2261/3223 , C08G2261/3324 , C08G2261/417 , C08G2261/418 , C08L65/00
摘要： A polyalkylthiophene block copolymer, a conductive composition including the same, a polymer-catalyst complex in which a polyalkylthiophene and a transition metal catalyst are connected, and a method of preparing a conductive block copolymer from the polymer-catalyst complex through a ring-opening metathesis reaction are provided.
摘要翻译：聚烷基噻吩嵌段共聚物，包含它们的导电组合物，其中连接有聚烷基噻吩和过渡金属催化剂的聚合物 - 催化剂络合物，以及由聚合物 - 催化剂配合物通过开环复分解剂制备导电嵌段共聚物的方法提供反应。

2. 发明授权

US06838341B2 Method for fabricating semiconductor device with self-aligned storage node 失效
标题翻译：用于制造具有自对准存储节点的半导体器件的方法
公开(公告)号：US06838341B2
公开(公告)日：2005-01-04
申请号：US10688079
申请日：2003-10-16
申请人： Jae-Man Yoon , Yun-Jae Lee , Sang-Hyun Lee , Wook-Je Kim
发明人： Jae-Man Yoon , Yun-Jae Lee , Sang-Hyun Lee , Wook-Je Kim
IPC分类号： H01L21/02 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10814 , H01L21/76802 , H01L21/76897 , H01L27/10855 , H01L28/91
摘要： A method for fabricating a semiconductor device includes preparing a semiconductor substrate having a contact pad; forming a first insulating film having a storage node contact exposing the contact pad and having a stack structure of an upper interlayer insulating film, a bottom interlayer insulating film, and an etching stopper between the upper and bottom interlayer insulating layers that protrudes into the storage node contact; forming a first conductive film for a storage node on the substrate; forming a second insulating film where a portion of a surface corresponding to the storage node contact is recessed; forming an etching mask layer on the recessed portion of the second insulating film; etching the second insulating film using the etching mask layer; forming a second conductive film for a storage node on the substrate; etching the first and second conductive films to isolate nodes; and removing the etching mask layer, the second insulating film and the upper interlayer insulating film.

3. 发明申请

US20180258672A1 AUTOMOTIVE DOOR HAVING INTERIOR DOOR HANDLE FOR PREVENTING ACCIDENT 审中-公开
公开(公告)号：US20180258672A1
公开(公告)日：2018-09-13
申请号：US15979618
申请日：2018-05-15
申请人： Yun Jae Lee
发明人： Yun Jae LEE , Go eun LEE , Si eun LEE
IPC分类号： E05B85/12
CPC分类号： E05B85/12
摘要： Provided is an automotive door having an interior door handle for preventing an accident. The door handle is connected to a rod to control operation of a door lock assembly inside a vehicle and is disposed on a door of the vehicle at a position corresponding to the shoulder of an adult sitting in the vehicle. Since the door handle is disposed on a door at a position corresponding to the shoulder of an adult sitting in the vehicle, when a passenger opens a door to exit a vehicle, his/her body is naturally turned back, so his/her eyes also naturally face the rear area. Accordingly, a collision with another vehicle, a motorcycle, or a bicycle approaching from behind can be prevented. Further, since the passenger looks back every time he/she opens a door, his/her consciousness about a safety accident when opening a door is increased.

4. 发明授权

US09123892B2 Polymer blend composition and actuators using the same 有权
标题翻译：聚合物共混组合物和使用其的致动器
公开(公告)号：US09123892B2
公开(公告)日：2015-09-01
申请号：US13466292
申请日：2012-05-08
申请人： Chong-Min Koo , Soon-Man Hong , Kyung-Youl Baek , Seung-Sang Hwang , Youn-Duk Park , Kyung-Ho Min , Jin-Hong Lee , Yun-Jae Lee , Ji-Young Jung , Jang-Woo Lee
发明人： Chong-Min Koo , Soon-Man Hong , Kyung-Youl Baek , Seung-Sang Hwang , Youn-Duk Park , Kyung-Ho Min , Jin-Hong Lee , Yun-Jae Lee , Ji-Young Jung , Jang-Woo Lee
IPC分类号： H01L41/18 , C08L53/00 , H01L41/193 , C08L27/16 , C08J5/18
CPC分类号： H01L41/193 , C08J5/18 , C08L27/16 , C08L53/00
摘要： The present invention relates to a polymer blend composition comprising a dielectric elastomer, an actuator film manufactured using the same, and an actuator comprising the film. The polymer blend composition according to the present invention comprises a block copolymer having excellent compatibility with the dielectric elastomer and excellent dielectric properties, and thus displacement values suitable for the purpose can be obtained by a simple method of adjusting a composition of the polymer blend. Moreover, the film manufactured using the same has high dielectric constant, low dielectric loss and high electromechanical displacement, and thus the film exhibits excellent dielectric properties when it is applied in a dielectric layer for an actuator.
摘要翻译：本发明涉及一种聚合物共混组合物，其包含介电弹性体，使用其制造的致动膜，以及包括该膜的致动器。根据本发明的聚合物共混物组合物包含与介电弹性体具有优异的相容性和优异的介电性能的嵌段共聚物，因此通过调节聚合物共混物的组成的简单方法可以获得适合于该目的的位移值。此外，使用其制造的膜具有高介电常数，低介电损耗和高机电位移，因此当其用于致动器的电介质层时，该膜表现出优异的介电性能。

5. 发明授权

US09087977B2 Semiconductor device having pinned layer with enhanced thermal endurance 有权
标题翻译：具有增强耐热性的固定层的半导体器件
公开(公告)号：US09087977B2
公开(公告)日：2015-07-21
申请号：US14254871
申请日：2014-04-16
申请人： Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
发明人： Jeong-Heon Park , Ki-Woong Kim , Hee-Ju Shin , Joon-Myoung Lee , Woo-Jin Kim , Jae-Hoon Kim , Se-Chung Oh , Yun-Jae Lee
IPC分类号： H01L43/02 , H01L43/08 , H01F10/32 , G11C11/16
CPC分类号： H01L43/02 , G11C11/161 , H01F10/30 , H01F10/32 , H01F10/3254 , H01F10/3272 , H01L23/528 , H01L27/222 , H01L43/08 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
摘要翻译：提供了具有彼此间隔开的自由层和钉扎层的半导体器件。在自由层和钉扎层之间形成隧道势垒层。被钉扎层可以包括下钉扎层和与下钉扎层隔开的上钉扎层。可以在下钉扎层和上钉扎层之间形成间隔件。非磁性接合层可以邻近间隔物设置在上或下钉扎层中的层之间。

6. 发明申请

US20130344437A1 PHOTOSENSITIVE RESIN COMPOSITION 有权
标题翻译：感光树脂组合物
公开(公告)号：US20130344437A1
公开(公告)日：2013-12-26
申请号：US13574354
申请日：2010-11-19
申请人： Pil Rye Yang , Kyung Keun Yoon , Yun Jae Lee
发明人： Pil Rye Yang , Kyung Keun Yoon , Yun Jae Lee
IPC分类号： G03F7/028
CPC分类号： G03F7/028 , G03F7/0007 , G03F7/038 , G03F7/0758
摘要： Disclosed is a photosensitive resin composition for an organic insulating layer. More specifically, the photosensitive resin composition is suitable for forming a substrate of a transflective thin film transistor liquid crystal display (TFT-LCD) or a pattern of an interlayer insulating layer by improving remarkably a pattern property with a high taper angle besides improvement of flatness, sensitivity, heat resistance, and transparency. Particularly, the photosensitive resin composition can provide low power dissipation besides a wide viewing angle and high visibility when being applied to a transflective type display. In addition, the photosensitive resin composition can provide a clear screen under natural light without a backlight by maintaining the brightness of a screen and prominent field visibility.
摘要翻译：公开了一种有机绝缘层用感光性树脂组合物。更具体地，感光性树脂组合物适合于通过除了改善平坦度以外，通过显着提高具有高锥角的图案特性来形成透反射薄膜晶体管液晶显示器（TFT-LCD）的基板或层间绝缘层的图案，灵敏度，耐热性和透明度。特别是，当应用于半透反射型显示器时，感光性树脂组合物除了具有广视角和高可见度外，还能够提供低功耗。此外，感光性树脂组合物可以通过保持屏幕的亮度和突出的视场可视性而在自然光下提供无背光的清晰屏幕。

7. 发明申请

US20120286627A1 POLYMER BLEND COMPOSITION AND ACTUATORS USING THE SAME 有权
标题翻译：聚合物混合组合物和使用它的致动器
公开(公告)号：US20120286627A1
公开(公告)日：2012-11-15
申请号：US13466292
申请日：2012-05-08
申请人： Chong-Min KOO , Soon-Man HONG , Kyung-Youl BAEK , Seung-Sang HWANG , Youn-Duk PARK , Kyung-Ho MIN , Jin-Hong LEE , Yun-Jae LEE , Ji-Young JUNG , Jang-Woo LEE
发明人： Chong-Min KOO , Soon-Man HONG , Kyung-Youl BAEK , Seung-Sang HWANG , Youn-Duk PARK , Kyung-Ho MIN , Jin-Hong LEE , Yun-Jae LEE , Ji-Young JUNG , Jang-Woo LEE
IPC分类号： H01L41/18 , C08L53/00
CPC分类号： H01L41/193 , C08J5/18 , C08L27/16 , C08L53/00
摘要： The present invention relates to a polymer blend composition comprising a dielectric elastomer, an actuator film manufactured using the same, and an actuator comprising the film. The polymer blend composition according to the present invention comprises a block copolymer having excellent compatibility with the dielectric elastomer and excellent dielectric properties, and thus displacement values suitable for the purpose can be obtained by a simple method of adjusting a composition of the polymer blend. Moreover, the film manufactured using the same has high dielectric constant, low dielectric loss and high electromechanical displacement, and thus the film exhibits excellent dielectric properties when it is applied in a dielectric layer for an actuator.
摘要翻译：本发明涉及一种聚合物共混组合物，其包含介电弹性体，使用其制造的致动膜，以及包括该膜的致动器。根据本发明的聚合物共混物组合物包含与介电弹性体具有优异的相容性和优异的介电性能的嵌段共聚物，因此通过调节聚合物共混物的组成的简单方法可以获得适合于该目的的位移值。此外，使用其制造的膜具有高介电常数，低介电损耗和高机电位移，因此当其用于致动器的电介质层时，该膜表现出优异的介电性能。

8. 发明授权

US06607983B1 Method of processing a defect source at a wafer edge region in a semiconductor manufacturing 失效
标题翻译：在半导体制造中在晶片边缘区域处理缺陷源的方法
公开(公告)号：US06607983B1
公开(公告)日：2003-08-19
申请号：US09707353
申请日：2000-11-06
申请人： Kwang-Youl Chun , Yun-Jae Lee , Won-Seong Lee , Jeong-Hoon Oh , Kyu-Hyun Lee
发明人： Kwang-Youl Chun , Yun-Jae Lee , Won-Seong Lee , Jeong-Hoon Oh , Kyu-Hyun Lee
IPC分类号： H01L21461
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/76802 , H01L21/76838 , H01L27/10852 , H01L27/10894 , H01L28/91
摘要： The present invention provides a method of eliminating or covering a defect source in a wafer edge region for semiconductor fabrication. During the etching process of a sacrificial oxide layer for storage node openings, the sacrificial oxide layer has a rumple topology in the wafer edge region due to etching non-uniformity of a photoresist layer formed on the sacrificial oxide layer. Subsequent deposition of a conductive layer and planarization etching, the conductive layer undesirably remains at the wafer edge region as a defect source. Such conductive contaminant particles dislodge, causing many problems in the wafer main region. The present invention removes such a defect source via two methods. One is to directly remove the defect source using a photoresist pattern exposing thereof. The other is to fix the defect source in place in the wafer edge region by protecting thereof by a photoresist pattern during subsequent cleaning processes.
摘要翻译：本发明提供一种消除或覆盖用于半导体制造的晶片边缘区域中的缺陷源的方法。在用于存储节点开口的牺牲氧化物层的蚀刻工艺期间，由于蚀刻在牺牲氧化物层上形成的光致抗蚀剂层的不均匀性，牺牲氧化物层在晶片边缘区域中具有隆起的拓扑结构。随后沉积导电层和平坦化蚀刻，导电层不期望地保留在晶片边缘区域作为缺陷源。这种导电性污染物颗粒移动，在晶片主区域引起许多问题。本发明通过两种方法去除这种缺陷源。一个是使用其曝光的光致抗蚀剂图案直接去除缺陷源。另一种是通过在随后的清洁过程中通过光致抗蚀剂图案的保护来将缺陷源固定在晶片边缘区域中。

9. 外观设计

USD781858S1 Data input device for computer 有权
公开(公告)号：USD781858S1
公开(公告)日：2017-03-21
申请号：US29518338
申请日：2015-02-23
申请人： Yun Jae Lee , Goonies Co., Ltd.
设计人： Yun Jae Lee

10. 发明申请

US20150280108A1 SEMICONDUCTOR DEVICE HAVING PINNED LAYER WITH ENHANCED THERMAL ENDURANCE 有权
公开(公告)号：US20150280108A1
公开(公告)日：2015-10-01
申请号：US14741446
申请日：2015-06-16
申请人： JEONG-HEON PARK , KI-WOONG KIM , HEE-JU SHIN , JOON-MYOUNG LEE , WOO-JIN KIM , JAE-HOON KIM , SE-CHUNG OH , YUN-JAE LEE
发明人： JEONG-HEON PARK , KI-WOONG KIM , HEE-JU SHIN , JOON-MYOUNG LEE , WOO-JIN KIM , JAE-HOON KIM , SE-CHUNG OH , YUN-JAE LEE
IPC分类号： H01L43/02 , H01L27/22 , H01L23/528 , H01L43/08
CPC分类号： H01L43/02 , G11C11/161 , H01F10/30 , H01F10/32 , H01F10/3254 , H01F10/3272 , H01L23/528 , H01L27/222 , H01L43/08 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

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