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1. 发明授权

US07101769B2 Method of forming a reliable high performance capacitor using an isotropic etching process 有权
标题翻译：使用各向同性蚀刻工艺形成可靠的高性能电容器的方法
公开(公告)号：US07101769B2
公开(公告)日：2006-09-05
申请号：US10776546
申请日：2004-02-10
申请人： Seung-Beom Kim , Won-Mo Park , Yun-Jae Lee , Joon-Mo Kwon , Myoung-Hee Han , Man-Jong Yu
发明人： Seung-Beom Kim , Won-Mo Park , Yun-Jae Lee , Joon-Mo Kwon , Myoung-Hee Han , Man-Jong Yu
IPC分类号： H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Disclosed herein is a method of forming a reliable high performance capacitor using an isotropic etching process to optimize the surface area of the lower electrodes while preventing an electrical bridge from forming between the lower electrodes. This method includes multiple sacrificial oxide layers that are formed over a substrate, an insulating layer with contact plugs, and an etch stopping layer. The sacrificial oxide layers are patterned and additionally isotropically etched to form an expanded capacitor hole. An exposed portion of the etch stopping layer is then etched to form a final capacitor hole exposing an upper portion of the contact plug and a portion of the insulating layer adjacent thereto. The semiconductor substrate having the final capacitor hole is cleaned to remove a native oxide film on the exposed upper portion of the contact plug.
摘要翻译：本文公开了一种使用各向同性蚀刻工艺形成可靠的高性能电容器的方法，以优化下电极的表面积，同时防止在下电极之间形成电桥。该方法包括在衬底上形成的多个牺牲氧化物层，具有接触插塞的绝缘层和蚀刻停止层。将牺牲氧化物层图案化并另外进行各向同性蚀刻以形成扩大的电容器孔。然后蚀刻停止层的暴露部分以形成露出接触插塞的上部和与其相邻的绝缘层的一部分的最终电容器孔。清洁具有最终电容器孔的半导体衬底以去除接触插塞的暴露的上部上的自然氧化膜。

2. 发明授权

US07323746B2 Recess gate-type semiconductor device and method of manufacturing the same 失效
标题翻译：嵌入式门式半导体器件及其制造方法
公开(公告)号：US07323746B2
公开(公告)日：2008-01-29
申请号：US11228041
申请日：2005-09-14
申请人： Won-Mo Park , Jae-Choel Paik , Du-Heon Song , Dong-Hyun Kim , Chang-Sub Lee
发明人： Won-Mo Park , Jae-Choel Paik , Du-Heon Song , Dong-Hyun Kim , Chang-Sub Lee
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L29/0692 , H01L29/4236
摘要： A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.
摘要翻译：凹槽型半导体器件包括具有至少部分地覆盖有源区中的凹槽的凹部的栅电极和设置在有源区中的由栅电极分离的源/漏区。所述凹槽在第一方向上与器件隔离区的侧壁分离，并沿着第二方向接触器件隔离区的侧壁。有源区在第二方向上的凹槽的宽度可以大于第二方向上的源极/漏极区的宽度，并且栅电极的凹陷部分可以具有在其角部沿第一方向突出的突出部。因此，半导体器件具有优异的结漏电流和优异的刷新特性。

3. 发明授权

US08633565B2 Semiconductor device including fuse having form of capacitor 有权
标题翻译：包括具有电容器形式的熔丝的半导体装置
公开(公告)号：US08633565B2
公开(公告)日：2014-01-21
申请号：US12840375
申请日：2010-07-21
申请人： Ho-Ju Song , Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim
发明人： Ho-Ju Song , Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim
IPC分类号： H01L29/93
CPC分类号： H01L23/5256 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.
摘要翻译：半导体器件包括具有电容器形式的熔丝。半导体器件包括形成在半导体衬底上的阴极，阴极上形成的阳极，以及形成在阴极和阳极之间并且电连接阴极和阳极的至少一个具有圆柱壳形状的灯丝。

4. 发明授权

US08058678B2 Semiconductor memory device including a cylinder type storage node and a method of fabricating the same 失效
标题翻译：包括圆柱型存储节点的半导体存储器件及其制造方法
公开(公告)号：US08058678B2
公开(公告)日：2011-11-15
申请号：US12537461
申请日：2009-08-07
申请人： Gil-Sub Kim , Won-Mo Park , Seong-Ho Kim , Dong-Kwan Yang
发明人： Gil-Sub Kim , Won-Mo Park , Seong-Ho Kim , Dong-Kwan Yang
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Provided is a semiconductor memory device including cylinder type storage nodes and a method of fabricating the semiconductor memory device. The semiconductor memory device includes: a semiconductor substrate including switching devices; a recessed insulating layer including storage contact plugs therein, wherein the storage contact plugs are electrically connected to the switching devices and the recessed insulating layer exposes at least some portions of upper surfaces and side surfaces of the storage contact plugs. The semiconductor device further includes cylinder type storage nodes each having a lower electrode. The lower electrode contacting the at least some portions of the exposed upper surfaces and side surfaces of the storage node contact plugs.
摘要翻译：提供了一种包括圆筒型存储节点的半导体存储器件和制造半导体存储器件的方法。半导体存储器件包括：包括开关器件的半导体衬底; 其中包括存储接触插塞的凹陷绝缘层，其中所述存储接触插塞电连接到所述开关装置，并且所述凹陷绝缘层暴露所述存储接触插塞的上表面和侧表面的至少一些部分。半导体器件还包括各自具有下电极的圆筒型存储节点。下部电极接触存储节点接触插塞的暴露的上表面和侧表面的至少一些部分。

5. 发明申请

US20100187101A1 METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20100187101A1
公开(公告)日：2010-07-29
申请号：US12691967
申请日：2010-01-22
申请人： Gil-Sub Kim , Won-Mo Park , Seong-Ho Kim , Dong-Kwan Yang , Ho-Ju Song
发明人： Gil-Sub Kim , Won-Mo Park , Seong-Ho Kim , Dong-Kwan Yang , Ho-Ju Song
IPC分类号： C23C14/34
CPC分类号： H01L27/10817 , H01L28/90
摘要： In a semiconductor device and a method of manufacturing the semiconductor device, lower electrodes having cylindrical shapes are provided to be arranged repeatedly on a substrate. Upper surfaces of the lower electrodes are flat so that the lower electrodes have uniform heights. Supporting structures are provided between the lower electrodes to support the lower electrode, the supporting structure partially contacting outer surfaces of sidewalls of the lower electrodes that are arranged in a line. A dielectric layer is formed on surfaces of the lower electrodes and the supporting structures. An upper electrode is provided on the dielectric layer. The semiconductor device includes a capacitor having an improved capacitance. Further, the capacitor includes the support structure between the lower electrodes to prevent the adjacent lower electrodes from being short each other.
摘要翻译：在半导体器件和半导体器件的制造方法中，具有圆筒形状的下电极被重复配置在基板上。下电极的上表面是平坦的，使得下电极具有均匀的高度。在下部电极之间设置支撑结构以支撑下部电极，支撑结构部分地接触一排地布置在下部电极的侧壁的外表面。在下电极和支撑结构的表面上形成电介质层。在电介质层上设置上电极。半导体器件包括具有改善的电容的电容器。此外，电容器包括在下电极之间的支撑结构，以防止相邻的下电极彼此短路。

6. 发明授权

US07393742B2 Semiconductor device having a capacitor and a fabrication method thereof 有权
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US07393742B2
公开(公告)日：2008-07-01
申请号：US11357832
申请日：2006-02-17
申请人： Won-Mo Park
发明人： Won-Mo Park
IPC分类号： H01L21/8242
CPC分类号： H01L27/10855 , H01L28/90
摘要： In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate and an insulating layer on the semiconductor substrate, a contact plug electrically connected to the semiconductor substrate and formed in the contact hole, a buffer conductive layer pattern electrically connected to the contact plug and formed on the insulating layer and the contact plug, an etching stopping layer formed on the buffer conductive layer pattern, a gap between the buffer conductive layer pattern and the etching stopping layer, a capacitor lower electrode electrically connected to the buffer conductive layer pattern and formed on the buffer conductive layer pattern. The gap is filled by a portion of the capacitor lower electrode.
摘要翻译：在具有电容器的半导体器件及其制造方法中，半导体器件包括在半导体衬底上的半导体衬底和绝缘层，电连接到半导体衬底并形成在接触孔中的接触插塞，缓冲导电电连接到接触插塞并形成在绝缘层和接触插塞上的层间图案，形成在缓冲导电层图案上的蚀刻停止层，缓冲导电层图案和蚀刻停止层之间的间隙，电容器下电极电连接到缓冲导电层图案并形成在缓冲导电层图案上。间隙由电容器下电极的一部分填充。

7. 发明授权

US08759945B2 Fuse structures, e-fuses comprising fuse structures, and semiconductor devices comprising e-fuses 有权
标题翻译：保险丝结构，包括保险丝结构的电子保险丝以及包括电子保险丝的半导体器件
公开(公告)号：US08759945B2
公开(公告)日：2014-06-24
申请号：US13081949
申请日：2011-04-07
申请人： Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim , Ho-Ju Song
发明人： Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim , Ho-Ju Song
IPC分类号： H01L23/52 , H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.
摘要翻译：公开了一种熔丝结构，包括熔丝结构的电熔丝和包括该电熔丝的半导体器件。熔丝结构包括第一和第二电极，第一和第二电极沿第一方向延伸，彼此隔开预定的距离并且其一端面对彼此，形成在第一电极的一端和第一电极的一端之间的绝缘层第二电极彼此面对，并且导电膜在绝缘层上重叠第一和第二电极的部分，并与第一电极和第二电极的一端接触。

8. 发明申请

US20110298086A1 Fuse Structures, E-Fuses Comprising Fuse Structures, and Semiconductor Devices Comprising E-Fuses 有权
标题翻译：保险丝结构，包括保险丝结构的电子保险丝以及包含电子保险丝的半导体器件
公开(公告)号：US20110298086A1
公开(公告)日：2011-12-08
申请号：US13081949
申请日：2011-04-07
申请人： Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim , Ho-Ju Song
发明人： Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim , Ho-Ju Song
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, an e-fuse including the fuse structure and a semiconductor device including the e-fuse are disclosed. The fuse structure includes first and second electrodes extending in a first direction, and spaced a predetermined distance apart from each other and having one ends thereof facing each other, an insulation layer formed between the one end of the first electrode and the one end of the second electrode facing each other, and a conductive film overlapping portions of the first and second electrodes on the insulation layer and contacting the first electrode and the one end of the second electrode.
摘要翻译：公开了一种熔丝结构，包括熔丝结构的电熔丝和包括该电熔丝的半导体器件。熔丝结构包括第一和第二电极，第一和第二电极沿第一方向延伸，彼此隔开预定的距离并且其一端面对彼此，形成在第一电极的一端和第一电极的一端之间的绝缘层第二电极彼此面对，并且导电膜在绝缘层上重叠第一和第二电极的部分，并与第一电极和第二电极的一端接触。

9. 发明申请

US20110049670A1 Semiconductor Device Including Fuse Having Form of Capacitor 有权
标题翻译：包括具有电容器形式的保险丝的半导体器件
公开(公告)号：US20110049670A1
公开(公告)日：2011-03-03
申请号：US12840375
申请日：2010-07-21
申请人： Ho-Ju Song , Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim
发明人： Ho-Ju Song , Seong-Ho Kim , Won-Mo Park , Gil-Sub Kim
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01L27/105 , H01L27/10852 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a fuse having the form of a capacitor. The semiconductor device includes a cathode formed on a semiconductor substrate, an anode formed over the cathode, and at least one filament having a cylindrical-shell shape formed between the cathode and the anode and electrically connecting the cathode and the anode.
摘要翻译：半导体器件包括具有电容器形式的熔丝。半导体器件包括形成在半导体衬底上的阴极，阴极上形成的阳极，以及形成在阴极和阳极之间并且电连接阴极和阳极的至少一个具有圆柱壳形状的灯丝。

10. 发明授权

US07564135B2 Semiconductor device having self-aligned contact and method of fabricating the same 有权
标题翻译：具有自对准接触的半导体器件及其制造方法
公开(公告)号：US07564135B2
公开(公告)日：2009-07-21
申请号：US11420203
申请日：2006-05-24
申请人： Won-Mo Park
发明人： Won-Mo Park
IPC分类号： H01L23/528
CPC分类号： H01L27/10888 , H01L21/76897 , H01L27/10814 , H01L28/40
摘要： A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.
摘要翻译：半导体器件包括布置在衬底上的导电图案，设置在衬底上的第一层间介质层和导电图案，设置在第一层间电介质层上并部分地与导电图案重叠的第一虚设图案，设置在第二层间介电层在第一层间介电层和第一虚设图案上，设置在第二层间电介质层上并部分地与导电图案重叠的第二虚设图案，设置在第二层间介电层和第二虚设图案上的第三层间介电层，以及接触插塞，其穿过第三层间电介质层，第二层间电介质层和第一层间电介质层以接触导电图案，接触插塞布置在第一虚设图案和第二虚设图案之间，接触插塞邻接第一虚拟模式和第二个哑拍燕鸥

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