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1. 发明授权

US08394697B2 Methods of forming capacitors for semiconductor memory devices 有权
标题翻译：形成半导体存储器件电容器的方法
公开(公告)号：US08394697B2
公开(公告)日：2013-03-12
申请号：US13010297
申请日：2011-01-20
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

2. 发明申请

US20120052647A1 Method Of Fabricating Semiconductor Device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120052647A1
公开(公告)日：2012-03-01
申请号：US13194030
申请日：2011-07-29
申请人： Kyu-Tae Kim , Jong-Seo Hong , Tae-Han Kim
发明人： Kyu-Tae Kim , Jong-Seo Hong , Tae-Han Kim
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28114 , H01L21/28238 , H01L29/42376 , H01L29/4966 , H01L29/66553 , H01L29/66628 , H01L29/7834
摘要： A method for fabricating a semiconductor device is disclosed. One embodiment of the method includes forming a dummy gate pattern on a substrate, forming an interlayer dielectric film that covers the dummy gate pattern, exposing a top surface of the dummy gate pattern, selectively removing the dummy gate pattern to form a first gate trench, forming a sacrificial layer pattern over a top surface of the substrate in the first gate trench, the sacrificial layer pattern leaving a top portion of the first gate trench exposed, increasing an upper width of the exposed top portion of the first gate trench to form a second gate trench, and removing the sacrificial layer pattern in the second gate trench, and forming a non-dummy gate pattern in the second gate trench.
摘要翻译：公开了一种制造半导体器件的方法。该方法的一个实施例包括在衬底上形成伪栅极图案，形成覆盖伪栅极图案的层间电介质膜，暴露伪栅极图案的顶表面，选择性地去除伪栅极图案以形成第一栅极沟槽，在所述第一栅极沟槽中的所述衬底的顶表面上形成牺牲层图案，所述牺牲层图案离开所述第一栅极沟槽的顶部部分而暴露，从而增加所述第一栅极沟槽的暴露顶部的上部宽度，以形成第二栅极沟槽，并且去除第二栅极沟槽中的牺牲层图案，以及在第二栅极沟槽中形成非虚拟栅极图案。

3. 发明申请

US20090068809A1 SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL ETCH STOPPER AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有本地止动器的半导体存储器件及其制造方法
公开(公告)号：US20090068809A1
公开(公告)日：2009-03-12
申请号：US12267785
申请日：2008-11-10
申请人： Jung-woo SEO , Jong-seo HONG , Tae-hyuk AHN , Jeong-sic JEON , Jun-sik HONG , Young-sun CHO
发明人： Jung-woo SEO , Jong-seo HONG , Tae-hyuk AHN , Jeong-sic JEON , Jun-sik HONG , Young-sun CHO
IPC分类号： H01L21/768 , H01L21/336
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

4. 发明申请

US20060146595A1 Methods for forming DRAM devices including protective patterns and related devices 失效
标题翻译：用于形成包括保护图案和相关装置的DRAM装置的方法
公开(公告)号：US20060146595A1
公开(公告)日：2006-07-06
申请号：US11327067
申请日：2006-01-06
申请人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
发明人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
IPC分类号： G11C11/00
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10855
摘要： A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
摘要翻译：在半导体衬底上形成第一层间电介质。接触焊盘被形成为通过第一层间电介质接触衬底。在第一层间电介质上形成位线不接触接触垫。形成第二层间电介质并将其平坦化以暴露位线的顶部。在所得结构的整个表面上形成保护层。在保护层上形成牺牲层。牺牲层，保护层和第二层间电介质在两个相邻的位线之间被图案化以形成露出接触焊盘的底部电极接触孔。形成导电层并平坦化以形成填充底部电极接触孔的底部电极接触塞。

5. 发明授权

US5476807A Method for forming fine patterns in a semiconductor device 失效
标题翻译：在半导体器件中形成精细图案的方法
公开(公告)号：US5476807A
公开(公告)日：1995-12-19
申请号：US227534
申请日：1994-04-14
申请人： Kang-hyun Lee , Jong-seo Hong , Hyoung-sub Kim , Jae-ho Kim , Min-seog Han
发明人： Kang-hyun Lee , Jong-seo Hong , Hyoung-sub Kim , Jae-ho Kim , Min-seog Han
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/10852 , H01L21/0337 , H01L28/88
摘要： A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF.sub.4, CHF.sub.4, and Ar gases, with the amount of the etch by-products being controllably adjusted by the ratio of these gases, and/or by controllably adjusting the time, temperature, and/or pressure parameters of this anisotropic etching process.
摘要翻译：一种用于形成精细图案的方法，例如，用于形成半导体存储器件的存储单元的电容器的存储电极，其包括以下步骤：在待图案化的层上沉积掩模层;在掩模上沉积光致抗蚀剂层层，图案化光致抗蚀剂层，从而形成光致抗蚀剂图案，使用光致抗蚀剂图案作为蚀刻掩模，各向异性地蚀刻掩模层，从而形成掩模层图案，其中在复合层的侧壁上形成蚀刻副产物由光致抗蚀剂图案和掩模层图案组成，并且使用复合层蚀刻待图案化层和蚀刻副产物作为蚀刻掩模，从而形成精细图案。掩模层由具有与光致抗蚀剂不同的物理性质的材料，例如高温氧化物制成。此外，各向异性蚀刻工艺优选通过使用CF 4，CHF 4和Ar气体的混合物的等离子体蚀刻工艺进行，其中蚀刻副产物的量可由这些气体的比例可控地调节，和/ 或通过可控地调节该各向异性蚀刻工艺的时间，温度和/或压力参数。

6. 发明授权

US07682778B2 Methods of forming contact plugs in semiconductor devices 失效
标题翻译：在半导体器件中形成接触插塞的方法
公开(公告)号：US07682778B2
公开(公告)日：2010-03-23
申请号：US11342560
申请日：2006-01-31
申请人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
发明人： Jung-Woo Seo , Tae-Hyuk Ahn , Jong-Seo Hong
IPC分类号： G03F7/16 , G03F7/40 , H01L21/027 , H01L21/441 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/31144 , G03F1/00 , H01L21/76897
摘要： Provided are contact photomasks and methods using such photomasks for fabricating semiconductor devices and forming contact plugs on portions of active regions exposed between gate lines. The elongated active regions are arrayed in a series of parallel groups with each group being, in turn, aligned along their longitudinal axes to form an acute angle with the gate lines. The contact photomask includes a plurality of openings arranged in parallel lines that are aligned at an angle offset from previously formed gate lines and which may be parallel to the active regions or may be aligned at an angle offset from the axes of both the groups of active regions and the gate lines. Processes for forming contact plugs using such photomasks may provide increased processing margin and extend the utility of conventional exposure equipment for semiconductor devices exhibiting increased integration density and/or built to more demanding design rules.
摘要翻译：提供了使用这种光掩模的接触光掩模和方法来制造半导体器件，并在暴露在栅极线之间的有源区域的部分上形成接触插塞。细长的有源区域被排列成一系列平行的组，每个组又沿它们的纵向轴线对准，以与栅极线形成锐角。接触光掩模包括以平行线布置的多个开口，其以与先前形成的栅极线偏移的角度排列，并且可以平行于有源区域，或者可以与两个活动组的轴线偏移的角度对准区域和栅极线。使用这种光掩模形成接触塞的方法可以提供增加的加工余量，并且扩展了展示增加的集成密度和/或构建到更苛刻的设计规则的半导体器件的常规曝光设备的效用。

7. 发明授权

US07648875B2 Methods for forming DRAM devices including protective patterns and related devices 失效
标题翻译：用于形成包括保护图案和相关装置的DRAM装置的方法
公开(公告)号：US07648875B2
公开(公告)日：2010-01-19
申请号：US11327067
申请日：2006-01-06
申请人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
发明人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10855
摘要： A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
摘要翻译：在半导体衬底上形成第一层间电介质。接触焊盘被形成为通过第一层间电介质接触衬底。在第一层间电介质上形成位线不接触接触垫。形成第二层间电介质并将其平坦化以暴露位线的顶部。在所得结构的整个表面上形成保护层。在保护层上形成牺牲层。牺牲层，保护层和第二层间电介质在两个相邻的位线之间被图案化以形成露出接触焊盘的底部电极接触孔。形成导电层并平坦化以形成填充底部电极接触孔的底部电极接触塞。

8. 发明授权

US07462899B2 Semiconductor memory device having local etch stopper and method of manufacturing the same 有权
标题翻译：具有局部蚀刻停止器的半导体存储器件及其制造方法
公开(公告)号：US07462899B2
公开(公告)日：2008-12-09
申请号：US11354175
申请日：2006-02-15
申请人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
发明人： Jung-woo Seo , Jong-seo Hong , Tae-hyuk Ahn , Jeong-sic Jeon , Jun-sik Hong , Young-sun Cho
IPC分类号： H01L27/108
CPC分类号： H01L21/76895 , H01L21/76837 , H01L21/76885 , H01L21/76897 , H01L27/10855 , H01L27/10888 , H01L27/10894
摘要： A semiconductor memory device includes a semiconductor substrate in which a cell region and a core and peripheral region are defined. The device further comprises isolation layers formed in the semiconductor substrate to define active regions, a first gate electrode structure formed in the cell region and a second gate electrode structure formed in the core and peripheral region. Source and drain regions formed in the active regions on respective sides of each of the gate electrode structures and self-aligned contact pads are formed in the cell region in contact with the source and drain regions. An insulating interlayer is formed on the semiconductor substrate between the self-aligned contact pads, and etch stoppers are formed on the insulating interlayer between the self-aligned contact pads in the cell region.
摘要翻译：半导体存储器件包括其中限定了单元区域和芯和外围区域的半导体衬底。该器件还包括形成在半导体衬底中以限定有源区的隔离层，形成在单元区域中的第一栅电极结构和形成在芯和外围区中的第二栅电极结构。形成在每个栅电极结构和自对准接触焊盘的相应侧上的有源区中的源区和漏区形成在与源区和漏区接触的单元区域中。在自对准接触焊盘之间的半导体衬底上形成绝缘中间层，并且在电池区域中的自对准接触焊盘之间的绝缘中间层上形成蚀刻阻挡层。

9. 发明授权

US08563412B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08563412B2
公开(公告)日：2013-10-22
申请号：US13204874
申请日：2011-08-08
申请人： Kyu-Tae Kim , Jong-Seo Hong
发明人： Kyu-Tae Kim , Jong-Seo Hong
IPC分类号： H01L21/3205
CPC分类号： H01L29/66545 , H01L21/28518 , H01L21/76831 , H01L21/76897 , H01L29/4966
摘要： A method of fabricating a semiconductor device includes forming gate patterns on a substrate, forming spacers on sidewalls of the gate patterns, forming a first capping insulation layer pattern on the gate patterns and the spacers, forming a second capping insulation layer pattern on the first capping insulation layer pattern, forming a passivation layer pattern filling contact holes between the gate patterns, removing the second capping insulation layer pattern while protecting the spacers using the passivation layer pattern, removing the passivation layer pattern to expose a top surface of the substrate, forming a silicide forming metal film on the surface of the substrate, and forming silicide patterns on the exposed top surface of the substrate.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，在栅极图案和间隔物上形成第一封盖绝缘层图案，在第一封盖上形成第二封盖绝缘层图案形成钝化层图案，填充栅极图案之间的接触孔，去除第二封盖绝缘层图案，同时使用钝化层图案保护间隔物，去除钝化层图案以暴露基板的顶表面，形成在衬底的表面上形成硅化物形成金属膜，并在衬底的暴露的顶表面上形成硅化物图案。

10. 发明申请

US20120052667A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120052667A1
公开(公告)日：2012-03-01
申请号：US13204874
申请日：2011-08-08
申请人： Kyu-Tae Kim , Jong-Seo Hong
发明人： Kyu-Tae Kim , Jong-Seo Hong
IPC分类号： H01L21/28
CPC分类号： H01L29/66545 , H01L21/28518 , H01L21/76831 , H01L21/76897 , H01L29/4966
摘要： A method of fabricating a semiconductor device includes forming gate patterns on a substrate, forming spacers on sidewalls of the gate patterns, forming a first capping insulation layer pattern on the gate patterns and the spacers, forming a second capping insulation layer pattern on the first capping insulation layer pattern, forming a passivation layer pattern filling contact holes between the gate patterns, removing the second capping insulation layer pattern while protecting the spacers using the passivation layer pattern, removing the passivation layer pattern to expose a top surface of the substrate, forming a silicide forming metal film on the surface of the substrate, and forming silicide patterns on the exposed top surface of the substrate.
摘要翻译：制造半导体器件的方法包括在衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，在栅极图案和间隔物上形成第一封盖绝缘层图案，在第一封盖上形成第二封盖绝缘层图案形成钝化层图案，填充栅极图案之间的接触孔，去除第二封盖绝缘层图案，同时使用钝化层图案保护间隔物，去除钝化层图案以暴露基板的顶表面，形成在衬底的表面上形成硅化物形成金属膜，并在衬底的暴露的顶表面上形成硅化物图案。

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