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1. 发明授权

US5476807A Method for forming fine patterns in a semiconductor device 失效
标题翻译：在半导体器件中形成精细图案的方法
公开(公告)号：US5476807A
公开(公告)日：1995-12-19
申请号：US227534
申请日：1994-04-14
申请人： Kang-hyun Lee , Jong-seo Hong , Hyoung-sub Kim , Jae-ho Kim , Min-seog Han
发明人： Kang-hyun Lee , Jong-seo Hong , Hyoung-sub Kim , Jae-ho Kim , Min-seog Han
IPC分类号： H01L21/302 , H01L21/02 , H01L21/033 , H01L21/3065 , H01L21/8242 , H01L21/00
CPC分类号： H01L27/10852 , H01L21/0337 , H01L28/88
摘要： A method for forming a fine pattern, e.g., for forming the storage electrodes of the capacitors of the memory cells of semiconductor memory devices, which includes the steps of depositing a mask layer on the layer to be patterned, depositing a photoresist layer on the mask layer, patterning the photoresist layer, to thereby form a photoresist pattern, anisotropically etching the mask layer, using the photoresist pattern as an etching mask, to thereby form a mask layer pattern, wherein etch by-products are formed on sidewalls of a composite layer comprised of the photoresist pattern and the mask layer pattern, and, etching the layer to be patterned using the composite layer and the etch by-products as an etching mask, to thereby form a fine pattern. The mask layer is made of a material, e.g., a high-temperature oxide, having different physical properties than that of the photoresist. Further, the anisotropic etching process is preferably carried out by means of a plasma etching process using a mixture of CF.sub.4, CHF.sub.4, and Ar gases, with the amount of the etch by-products being controllably adjusted by the ratio of these gases, and/or by controllably adjusting the time, temperature, and/or pressure parameters of this anisotropic etching process.
摘要翻译：一种用于形成精细图案的方法，例如，用于形成半导体存储器件的存储单元的电容器的存储电极，其包括以下步骤：在待图案化的层上沉积掩模层;在掩模上沉积光致抗蚀剂层层，图案化光致抗蚀剂层，从而形成光致抗蚀剂图案，使用光致抗蚀剂图案作为蚀刻掩模，各向异性地蚀刻掩模层，从而形成掩模层图案，其中在复合层的侧壁上形成蚀刻副产物由光致抗蚀剂图案和掩模层图案组成，并且使用复合层蚀刻待图案化层和蚀刻副产物作为蚀刻掩模，从而形成精细图案。掩模层由具有与光致抗蚀剂不同的物理性质的材料，例如高温氧化物制成。此外，各向异性蚀刻工艺优选通过使用CF 4，CHF 4和Ar气体的混合物的等离子体蚀刻工艺进行，其中蚀刻副产物的量可由这些气体的比例可控地调节，和/ 或通过可控地调节该各向异性蚀刻工艺的时间，温度和/或压力参数。

2. 发明授权

US06218690B1 Transistor having reverse self-aligned structure 有权
标题翻译：晶体管具有反向自对准结构
公开(公告)号：US06218690B1
公开(公告)日：2001-04-17
申请号：US09376041
申请日：1999-08-16
申请人： Hyoung-sub Kim , Ja-hum Ku , Chul-sung Kim , Jung-woo Park
发明人： Hyoung-sub Kim , Ja-hum Ku , Chul-sung Kim , Jung-woo Park
IPC分类号： H01L2976
CPC分类号： H01L29/66606 , H01L29/66621
摘要： A reverse self-aligned field effect transistor and a method of fabricating the same are provided. The reverse self-aligned transistor includes a source formed on an active region of a semiconductor substrate and a drain formed on the active region of the semiconductor substrate, the drain being positioned a predetermined distance from the source. A silicide film is formed on the source and the drain. Insulative film spacers are formed on sidewalls of a trench, the trench being formed by etchin the semiconductor substrate between the source and the drain. A gate insulative film is formed on a lower portion of the trench and a metal gate is formed on the gate insulative film between the insulative film spacers. The metal gate is electrically isolated from the source and the drain by the insulative film spacers.
摘要翻译：提供了反向自对准场效应晶体管及其制造方法。反向自对准晶体管包括形成在半导体衬底的有源区上的源极和形成在半导体衬底的有源区上的漏极，漏极位于与源极预定的距离处。在源极和漏极上形成硅化物膜。绝缘膜间隔物形成在沟槽的侧壁上，沟槽通过蚀刻在源极和漏极之间的半导体衬底形成。栅极绝缘膜形成在沟槽的下部，并且在绝缘膜间隔物上的栅极绝缘膜上形成金属栅极。金属栅极通过绝缘膜间隔物与源极和漏极电隔离。

3. 发明授权

US6051492A Method of manufacturing a wiring layer in semiconductor device 失效
标题翻译：制造半导体器件中的布线层的方法
公开(公告)号：US6051492A
公开(公告)日：2000-04-18
申请号：US758647
申请日：1996-11-27
申请人： Byung-lyul Park , Hyoung-sub Kim , Jung-min Ha
发明人： Byung-lyul Park , Hyoung-sub Kim , Jung-min Ha
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763 , H01L21/461
CPC分类号： H01L21/76843 , H01L21/76802 , H01L21/76826 , Y10S408/707
摘要： A method of manufacturing a metal wiring layer in a semiconductor device, wherein an insulating layer is plasma treated before a tungsten nitride film is formed on the insulating layer. A metal, metal silicide or metal alloy thereafter being deposited over the tungsten nitride film.
摘要翻译：一种在半导体器件中制造金属布线层的方法，其中在绝缘层上形成氮化钨膜之前，对绝缘层进行等离子体处理。之后沉积在氮化钨膜上的金属，金属硅化物或金属合金。

4. 发明授权

US5547889A Method of forming a semiconductor device having vertical conduction transistors and cylindrical cell gates 失效
标题翻译：形成具有垂直导电晶体管和圆柱形单元栅极的半导体器件的方法
公开(公告)号：US5547889A
公开(公告)日：1996-08-20
申请号：US442713
申请日：1995-05-08
申请人： Hyoung-sub Kim
发明人： Hyoung-sub Kim
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10823
摘要： A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars. Each of the silicon pillars includes vertically stacked layers which serve as respective drain, channel, and source regions of a transistor.
摘要翻译：具有垂直导电晶体管和圆柱形单元栅极的半导体器件，例如DRAM，其包括形成在半导体衬底中的多个间隔开的沟槽隔离区，形成在半导体衬底上的多个位线，形成的硅柱在每个位线上形成栅极绝缘层和形成在每个硅柱上的栅极线与其周围的关系，形成在栅极线中的凹槽中的平坦化层，形成在栅极线和平坦化层的上表面上的绝缘层，多个接触孔设置在绝缘层，栅极线和栅极绝缘层的垂直对齐部分中，位于硅柱之上，并且形成有电容器的存储节点，其形成有接触孔和相邻的表面部分绝缘层与各个硅柱的源极区域接触。每个硅柱包括用作晶体管的相应漏极，沟道和源极区的垂直层叠层。

5. 发明申请

US20150132942A1 METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES HAVING BURIED CONTACTS AND RELATED SEMICONDUCTOR DEVICES 有权
标题翻译：制造带有接触触点的半导体器件和相关半导体器件的方法
公开(公告)号：US20150132942A1
公开(公告)日：2015-05-14
申请号：US14538832
申请日：2014-11-12
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Ji-young Kim
IPC分类号： H01L21/768 , H01L21/321 , H01L21/3205 , H01L21/311
CPC分类号： H01L27/10823 , H01L21/31111 , H01L21/31144 , H01L21/76224 , H01L23/5226 , H01L23/528 , H01L23/53295 , H01L27/10814 , H01L27/10855 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: forming bit line structures spaced apart from each other by first groove disposed in first direction, extending in first direction, and spaced apart from each other in second direction perpendicular to first direction, on substrate in which word line is buried; forming multilayer spacer on both sidewalls of bit line structure; forming sacrificial layer to fill first groove; forming second grooves spaced apart from each other in first direction and second direction, by patterning sacrificial layer; etching outermost spacer of multilayer spacer located in second groove; forming first supplementary spacer in second groove; forming insulating layer to fill second groove; and forming third grooves spaced apart from each other in first direction and second direction, on both sides of first supplementary spacer, by removing sacrificial layer and insulating layer.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：通过在第一方向上布置的第一槽形成位线结构，该第一槽在第一方向上延伸，并且在垂直于第一方向的第二方向上彼此间隔开，在其中掩埋有字线的衬底上; 在位线结构的两个侧壁上形成多层间隔物; 形成牺牲层以填充第一凹槽; 通过图案化牺牲层形成在第一方向和第二方向上彼此间隔开的第二凹槽; 蚀刻位于第二凹槽中的多层间隔物的最外层间隔; 在第二槽中形成第一辅助间隔件; 形成绝缘层以填充第二凹槽; 以及通过去除牺牲层和绝缘层，在第一辅助隔离物的两侧上，在第一方向和第二方向上形成彼此间隔开的第三槽。

6. 发明授权

US09012321B1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09012321B1
公开(公告)日：2015-04-21
申请号：US14283666
申请日：2014-05-21
申请人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Nak-jin Son , Ji-young Kim
发明人： Dae-ik Kim , Hyoung-sub Kim , Yoo-sang Hwang , Nak-jin Son , Ji-young Kim
IPC分类号： H01L21/00 , H01L21/762 , H01L21/768
CPC分类号： H01L21/76224 , H01L21/743 , H01L27/10823 , H01L27/10876 , H01L27/10885 , H01L27/10891
摘要： Provided is a method of manufacturing a semiconductor device. The method includes forming a sacrificial film as part of a process of forming a semiconductor device. The sacrificial film has a relatively high etch selectivity with respect to other materials of the semiconductor device so as to reduce loss of etching masks and improve the quality of a components (e.g., buried contacts) of the semiconductor device.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成牺牲膜作为形成半导体器件的工艺的一部分。牺牲膜相对于半导体器件的其它材料具有相对高的蚀刻选择性，以便减少蚀刻掩模的损耗并提高半导体器件的部件（例如，埋入触点）的质量。

7. 发明申请

US20110017990A1 Thin-film transistor and method of manufacturing the same 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20110017990A1
公开(公告)日：2011-01-27
申请号：US12659153
申请日：2010-02-26
申请人： Kyoung-seok Son , Jang-yeon Kwon , Hyoung-sub Kim , Hoo-jeong Lee , Mi-ran Moon , Kyung Park
发明人： Kyoung-seok Son , Jang-yeon Kwon , Hyoung-sub Kim , Hoo-jeong Lee , Mi-ran Moon , Kyung Park
IPC分类号： H01L29/786 , H01L21/44
CPC分类号： H01L29/7869
摘要： Example embodiments relate to thin-film transistors (TFT) and methods for fabricating the same. A thin-film transistor according to example embodiments may include a gate, a gate insulation layer, a channel layer including a first oxide semiconductor layer and a second oxide semiconductor layer, and a source and drain on opposite sides of the channel layer. The first oxide semiconductor layer may have relatively large crystal grains compared to the second oxide semiconductor layer.
摘要翻译：示例性实施例涉及薄膜晶体管（TFT）及其制造方法。根据示例性实施例的薄膜晶体管可以包括栅极，栅极绝缘层，包括第一氧化物半导体层和第二氧化物半导体层的沟道层，以及在沟道层的相对侧上的源极和漏极。与第二氧化物半导体层相比，第一氧化物半导体层可以具有相对较大的晶粒。

8. 发明授权

US07057242B2 Transistor structures having access gates with narrowed central portions 有权
公开(公告)号：US07057242B2
公开(公告)日：2006-06-06
申请号：US10264136
申请日：2002-10-03
申请人： Ji-young Kim , Hyoung-sub Kim
发明人： Ji-young Kim , Hyoung-sub Kim
IPC分类号： H01L29/76
CPC分类号： H01L27/10873 , H01L21/28123 , H01L27/0207 , H01L29/1033 , H01L29/4238
摘要： An integrated circuit transistor includes an active region in a substrate, elongated along a first direction. A gate pattern is disposed on the substrate and crosses the active region along a second direction transverse to the first direction. The gate pattern includes an access gate portion disposed on the active region and narrowed at a central portion thereof. The gate pattern may further include a pass gate portion adjoining the access gate portion at the point beyond the edge of the active region, the pass gate portion having a lesser extent along the first direction than the access gate portion.

9. 发明授权

US5753562A Methods of forming semiconductor devices in substrates having inverted-trench isolation regions therein 失效
标题翻译：在其中具有反向沟槽隔离区的衬底中形成半导体器件的方法
公开(公告)号：US5753562A
公开(公告)日：1998-05-19
申请号：US766781
申请日：1996-12-13
申请人： Hyoung-sub Kim
发明人： Hyoung-sub Kim
IPC分类号： H01L21/76 , H01L21/762 , H01L29/78
CPC分类号： H01L21/76224 , Y10S438/977
摘要： Methods of forming semiconductor substrates having inverted-trench isolation regions therein include the steps of forming at least one trench in a semiconductor substrate at a first face thereof and then forming a stopping layer on the bottom of the trench. An etching or polishing step is then performed on a second face of the substrate which extends opposite the first face, until the stopping layer is exposed. Semiconductor devices are then formed in the remaining portions of the substrate extending adjacent sidewalls of the trench, at the polished second face. In particular, first and second trenches are preferably formed at a first face of a first semiconductor substrate and then respective first and second stopping layers comprising silicon nitride are formed on bottoms of the first and second trenches. First and second electrically insulating layers (e.g., SiO.sub.2) are then formed on the first and second stopping layers, to fill the first and second trenches. The electrically insulating layers are then polished using a chemical-mechanical polishing step to form a substantially planar surface to which a second substrate is preferably bonded. A second face of the first substrate, extending opposite the first face, is then polished until the stopping layers are exposed and a smooth semiconductor surface is defined extending between the first and second trenches. Semiconductor devices are then formed in the substrate, opposite the smooth semiconductor surface and between the insulation-filled trenches.
摘要翻译：形成其中具有反向沟槽隔离区域的半导体衬底的方法包括以下步骤：在半导体衬底的第一面处形成至少一个沟槽，然后在沟槽的底部形成阻挡层。然后在衬底的与第一面相对延伸的第二面上执行蚀刻或抛光步骤，直到暴露停止层。然后在抛光的第二面处，在衬底的相邻侧壁延伸的衬底的其余部分中形成半导体器件。特别地，第一和第二沟槽优选地形成在第一半导体衬底的第一面上，然后在第一和第二沟槽的底部形成包括氮化硅的各自的第一和第二阻挡层。然后在第一和第二停止层上形成第一和第二电绝缘层（例如SiO 2），以填充第一和第二沟槽。然后使用化学 - 机械抛光步骤对电绝缘层进行抛光，以形成基本上平坦的表面，优选地将第二衬底接合。然后抛光第一衬底的与第一面相对延伸的第二面，直到暴露停止层，并且限定平滑的半导体表面在第一和第二沟槽之间延伸。然后在衬底中形成半导体器件，与光滑半导体表面和绝缘填充沟槽相对。

10. 发明授权

US5574299A Semiconductor device having vertical conduction transistors and cylindrical cell gates 失效
公开(公告)号：US5574299A
公开(公告)日：1996-11-12
申请号：US442712
申请日：1995-06-29
申请人： Hyoung-sub Kim
发明人： Hyoung-sub Kim
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10823
摘要： A semiconductor device, e.g., a DRAM, having vertical conduction transistors and cylindrical cell gates, which includes a plurality of spaced-apart trench isolation regions formed in a semiconductor substrate, a plurality of bit lines formed on the semiconductor substrate, a silicon pillar formed on each bit line, a gate insulating layer and gate line formed on each silicon pillar in surrounding relationship thereto, a planarizing layer formed in recesses in the gate lines, an insulating layer formed on the upper surfaces of the gate line and planarizing layer, a plurality of contact holes provided in vertically aligned portions of the insulating layer, the gate line, and the gate insulating layer located above respective ones of the silicon pillars, and, a storage node of a capacitor formed with the contact holes and adjacent surface portions of the insulating layer, in contact with the source region of respective ones of the silicon pillars. Each of the silicon pillars includes vertically stacked layers which serve as respective drain, channel, and source regions of a transistor.

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