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1. 发明申请

US20060146595A1 Methods for forming DRAM devices including protective patterns and related devices 失效
标题翻译：用于形成包括保护图案和相关装置的DRAM装置的方法
公开(公告)号：US20060146595A1
公开(公告)日：2006-07-06
申请号：US11327067
申请日：2006-01-06
申请人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
发明人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
IPC分类号： G11C11/00
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10855
摘要： A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
摘要翻译：在半导体衬底上形成第一层间电介质。接触焊盘被形成为通过第一层间电介质接触衬底。在第一层间电介质上形成位线不接触接触垫。形成第二层间电介质并将其平坦化以暴露位线的顶部。在所得结构的整个表面上形成保护层。在保护层上形成牺牲层。牺牲层，保护层和第二层间电介质在两个相邻的位线之间被图案化以形成露出接触焊盘的底部电极接触孔。形成导电层并平坦化以形成填充底部电极接触孔的底部电极接触塞。

2. 发明授权

US07648875B2 Methods for forming DRAM devices including protective patterns and related devices 失效
标题翻译：用于形成包括保护图案和相关装置的DRAM装置的方法
公开(公告)号：US07648875B2
公开(公告)日：2010-01-19
申请号：US11327067
申请日：2006-01-06
申请人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
发明人： Jong-Seo Hong , Jung-Woo Seo , Jun-Sik Hong , Jeong-Sic Jeon
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10855
摘要： A first interlayer dielectric is formed on a semiconductor substrate. A contact pad is formed to contact the substrate through the first interlayer dielectric. A bitline is formed on the first interlayer dielectric not to contact the contact pad. A second interlayer dielectric is formed and planarized to expose the top of the bitline. A protective layer is formed an entire surface of the resultant structure. A sacrificial layer is formed on the protective layer. The sacrificial layer, the protective layer, and the second interlayer dielectric are patterned between two adjacent bitlines to form a bottom electrode contact hole exposing the contact pad. A conductive layer is formed and planarized to form a bottom electrode contact plug filling the bottom electrode contact hole.
摘要翻译：在半导体衬底上形成第一层间电介质。接触焊盘被形成为通过第一层间电介质接触衬底。在第一层间电介质上形成位线不接触接触垫。形成第二层间电介质并将其平坦化以暴露位线的顶部。在所得结构的整个表面上形成保护层。在保护层上形成牺牲层。牺牲层，保护层和第二层间电介质在两个相邻的位线之间被图案化以形成露出接触焊盘的底部电极接触孔。形成导电层并平坦化以形成填充底部电极接触孔的底部电极接触塞。

3. 发明授权

US08394697B2 Methods of forming capacitors for semiconductor memory devices 有权
标题翻译：形成半导体存储器件电容器的方法
公开(公告)号：US08394697B2
公开(公告)日：2013-03-12
申请号：US13010297
申请日：2011-01-20
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

4. 发明授权

US07888724B2 Capacitors for semiconductor memory devices 有权
标题翻译：半导体存储器件的电容器
公开(公告)号：US07888724B2
公开(公告)日：2011-02-15
申请号：US11316166
申请日：2005-12-22
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

5. 发明申请

US20110117715A1 Methods of Forming Capacitors For Semiconductor Memory Devices 有权
标题翻译：半导体存储器件形成电容器的方法
公开(公告)号：US20110117715A1
公开(公告)日：2011-05-19
申请号：US13010297
申请日：2011-01-20
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L21/02
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

6. 发明申请

US20060138513A1 Capacitors for semiconductor memory devices and methods of forming the same 有权
标题翻译：用于半导体存储器件的电容器及其形成方法
公开(公告)号：US20060138513A1
公开(公告)日：2006-06-29
申请号：US11316166
申请日：2005-12-22
申请人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
发明人： Jong-Seo Hong , Jeong-Sic Jeon , Chun-Suk Suh , Yoo-Sang Hwang
IPC分类号： H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： A capacitor of a semiconductor memory device, and methods of forming the same, are disclosed. A pad interlayer insulating layer is disposed on a semiconductor substrate of an active region. Landing pads and a central landing pad are disposed in peripheral portions and a central portion of the active region, respectively, to penetrate the pad interlayer insulating layer. The upper surface of the central landing pad has a different area from the upper surfaces of the landing pads. A buried interlayer insulating layer is formed on the pad interlayer insulating layer to cover the landing pads and the central landing pad. Buried plugs are formed on the respective landing pads to penetrate the buried interlayer insulating layer. Lower electrodes are formed on the buried plugs.
摘要翻译：公开了一种半导体存储器件的电容器及其形成方法。衬垫层间绝缘层设置在有源区的半导体衬底上。着陆垫和中央着陆垫分别设置在活动区域的周边部分和中心部分中，以穿透垫层间绝缘层。中央着陆垫的上表面与着陆垫的上表面具有不同的面积。掩埋层间绝缘层形成在焊盘层间绝缘层上，以覆盖着陆焊盘和中央着陆焊盘。在相应的着陆焊盘上形成埋入的插塞以穿透埋入的层间绝缘层。下电极形成在埋地塞上。

7. 发明申请

US20050042837A1 Method of controlling depth of trench in shallow trench isolation and method of forming trench for isolation using the same 审中-公开
标题翻译：在浅沟槽隔离中控制沟槽深度的方法以及使用其形成用于隔离的沟槽的方法
公开(公告)号：US20050042837A1
公开(公告)日：2005-02-24
申请号：US10916304
申请日：2004-08-10
申请人： Jun-Sik Hong , Jeong-Sic Jeon , Tae Ahn , Dong-Hyun Kim
发明人： Jun-Sik Hong , Jeong-Sic Jeon , Tae Ahn , Dong-Hyun Kim
IPC分类号： H01L21/3065 , H01L21/308 , H01L21/762 , H01L21/76 , H01L21/311
CPC分类号： H01L21/76224 , H01L21/3065 , H01L21/3081 , H01L21/3085
摘要： According to some embodiments of the invention, a method of controlling the depth of a trench includes forming a mask layer on a semiconductor substrate, forming a sacrificial layer on the mask layer using a material having an etch selectivity ranging from a 1:1 to a 3:1 ratio with respect to the semiconductor substrate, forming a sacrificial pattern and a mask pattern by removing a portion of the sacrificial layer and a portion of the mask layer so that an isolation region of the semiconductor substrate is exposed, and forming a trench in the isolation region of the semiconductor substrate by performing a main etch process using a point at which the top surface of the mask pattern is exposed as an etch stop point so that the sacrificial pattern and the isolation region of the semiconductor substrate are simultaneously etched.
摘要翻译：根据本发明的一些实施例，一种控制沟槽深度的方法包括：在半导体衬底上形成掩模层，在掩模层上形成牺牲层，该掩模层的蚀刻选择范围为1：1至相对于半导体衬底的比例为3:1，通过去除牺牲层的一部分和掩模层的一部分形成牺牲图案和掩模图案，使得半导体衬底的隔离区域暴露，并形成沟槽在半导体衬底的隔离区域中，通过使用暴露掩模图案的顶表面的点作为蚀刻停止点进行主蚀刻工艺，以使得半导体衬底的牺牲图案和隔离区域被同时蚀刻。

8. 发明授权

US06919640B2 Semiconductor device having a contact window including a lower region with a wider width to provide a lower contact resistance 失效
标题翻译：具有接触窗的半导体器件包括具有较宽宽度的下部区域以提供较低的接触电阻
公开(公告)号：US06919640B2
公开(公告)日：2005-07-19
申请号：US10823485
申请日：2004-04-12
申请人： Jeong-Sic Jeon , Jae-Woong Kim
发明人： Jeong-Sic Jeon , Jae-Woong Kim
IPC分类号： H01L21/28 , H01L21/311 , H01L21/461 , H01L21/768 , H01L23/485 , H01L23/522
CPC分类号： H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/76804 , H01L21/76831 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.
摘要翻译：提供具有接触窗的半导体器件及其制造方法。在半导体基板上依次形成下介电层，导电图案和上电介质层。下介电层具有比上介电层更高的各向同性蚀刻速率。通过各向异性蚀刻对上电介质层和下电介质层进行图案化以形成沟槽而不暴露半导体衬底。所得结构经受各向同性蚀刻以暴露衬底并且形成在下区域中具有比在上部区域中更宽的宽度的接触窗口，而不损坏半导体衬底。

9. 发明授权

US06753221B2 Methods for fabricating semiconductor devices having capacitors 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US06753221B2
公开(公告)日：2004-06-22
申请号：US10322274
申请日：2002-12-17
申请人： Jeong-Sic Jeon , Chang-Jin Kang , Seung-Young Son , Jin-Hong Kim
发明人： Jeong-Sic Jeon , Chang-Jin Kang , Seung-Young Son , Jin-Hong Kim
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L21/31116 , H01L21/32136 , H01L27/10894 , H01L28/55 , H01L28/91
摘要： Methods for fabricating semiconductor devices having capacitors are provided. A plurality of storage node electrodes are formed on a semiconductor substrate. Then, a capacitor dielectric layer is formed over the storage node electrodes. A plate electrode layer is subsequently formed on the capacitor dielectric layer. A hard mask layer is then formed on the resultant structure where the plate electrode layer is formed so as to fill a gap between the adjacent storage node electrodes. The hard mask layer and the plate electrode layer are successively patterned to form a plate electrode.
摘要翻译：提供了制造具有电容器的半导体器件的方法。多个存储节点电极形成在半导体衬底上。然后，在存储节点电极上形成电容器电介质层。随后在电容器电介质层上形成平板电极层。然后在其上形成平板电极层的所得结构上形成硬掩模层，以填充相邻存储节点电极之间的间隙。硬掩模层和平板电极层依次构图以形成平板电极。

10. 发明授权

US07001817B2 Method for fabricating a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07001817B2
公开(公告)日：2006-02-21
申请号：US10696417
申请日：2003-10-29
申请人： Sang-Won Yeo , Jeong-Sic Jeon , Chang-Jin Kang , Chang-Won Lee
发明人： Sang-Won Yeo , Jeong-Sic Jeon , Chang-Jin Kang , Chang-Won Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28176 , H01L29/4941 , H01L29/6656 , H01L29/6659
摘要： A method for fabricating a semiconductor device, including forming a gate insulating film and a gate electrode film on a semiconductor substrate, and patterning the gate electrode film to form a gate electrode. A portion of the gate insulating film is removed to form an undercut region beneath the gate electrode. A buffer silicon film is formed over an entire surface of the resultant substrate to cover the gate electrode and to fill the undercut region. The buffer silicon film is selectively oxidized to form a buffer silicon oxide film.
摘要翻译：一种制造半导体器件的方法，包括在半导体衬底上形成栅极绝缘膜和栅极电极膜，以及对栅电极膜进行构图以形成栅电极。去除栅极绝缘膜的一部分以在栅极电极下方形成底切区域。在所得基板的整个表面上形成缓冲硅膜以覆盖栅电极并填充底切区域。缓冲硅膜被选择性地氧化以形成缓冲氧化硅膜。

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