专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07544991B2 Non-volatile memory device and methods of manufacturing and operating the same 有权
标题翻译：非易失性存储器件及其制造和操作方法
公开(公告)号：US07544991B2
公开(公告)日：2009-06-09
申请号：US11698067
申请日：2007-01-26
申请人： Jin-Woo Kim , Jong-Hyon Ahn , Don-Woo Lee
发明人： Jin-Woo Kim , Jong-Hyon Ahn , Don-Woo Lee
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/42336 , H01L21/28273 , H01L27/115 , H01L27/11553 , H01L29/7885
摘要： A non-volatile memory device and methods of manufacturing and operating the same are provided. In a method of manufacturing a non-volatile memory device, a substrate having a stepped portion that may include a first horizontal face, a second horizontal face lower than the first horizontal face, and a vertical face connected between the first and second horizontal faces may be prepared. A first impurity region may be formed under the first horizontal face. A tunnel insulation layer may be continuously formed on the vertical face and the second horizontal face. A floating gate electrode having a tip higher than the first horizontal face may be formed on the tunnel insulation layer. A dielectric layer may be formed on the floating gate electrode. The floating gate electrode may be covered with a control gate electrode. A second impurity region horizontally spaced apart from the floating gate electrode may be formed under the second horizontal face.
摘要翻译：提供了一种非易失性存储器件及其制造和操作方法。在制造非易失性存储器件的方法中，具有阶梯部分的衬底可以包括第一水平面，比第一水平面低的第二水平面和连接在第一和第二水平面之间的垂直面，准备好可以在第一水平面下方形成第一杂质区。隧道绝缘层可以在垂直面和第二水平面上连续地形成。具有尖端高于第一水平面的浮栅电极可以形成在隧道绝缘层上。可以在浮栅电极上形成电介质层。浮栅电极可以用控制栅电极覆盖。可以在第二水平面下方形成与浮栅电极水平间隔开的第二杂质区域。

2. 发明申请

US20080087934A1 Nonvolatile memory device, method of fabricating and method of operating the same 有权
标题翻译：非易失存储器件，其制造方法及其操作方法
公开(公告)号：US20080087934A1
公开(公告)日：2008-04-17
申请号：US11589725
申请日：2006-10-31
申请人： Jong-hyon Ahn , Jin-woo Kim
发明人： Jong-hyon Ahn , Jin-woo Kim
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L21/28273 , H01L29/42324 , H01L29/7887
摘要： A nonvolatile memory device may include a semiconductor substrate; first and second floating gate electrodes formed on the semiconductor substrate; a control gate electrode formed on the first and second floating gate electrodes that may include a line body and a first leg, second leg, and third leg extending vertically from the line body toward the semiconductor substrate; and an inter-layer insulating film interposed between the semiconductor substrate and a lower end of the first leg and between the semiconductor substrate and a lower end of the second leg.
摘要翻译：非易失性存储器件可以包括半导体衬底; 形成在半导体衬底上的第一和第二浮栅电极; 形成在第一和第二浮栅上的控制栅电极，其可以包括线体和从线体向半导体衬底垂直延伸的第一腿，第二腿和第三腿; 以及介于所述半导体基板与所述第一支腿的下端之间以及所述半导体基板与所述第二支柱的下端之间的层间绝缘膜。

3. 发明申请

US20070187770A1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070187770A1
公开(公告)日：2007-08-16
申请号：US11705164
申请日：2007-02-12
申请人： Jong-hyon Ahn , Jae-cheol Yoo , Ki-seog Youn , Kwan-jong Roh , Su-gon Bae , Ki-young Kim
发明人： Jong-hyon Ahn , Jae-cheol Yoo , Ki-seog Youn , Kwan-jong Roh , Su-gon Bae , Ki-young Kim
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/11 , H01L27/1104 , H01L29/7843
摘要： A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
摘要翻译：半导体集成电路器件可以包括半导体衬底，半导体衬底上的静态存储单元，下拉晶体管上的拉伸应力膜以及通过晶体管上的压应力膜。静态存储单元可以包括形成锁存器的多个上拉晶体管和下拉晶体管，并且多通道晶体管可用于访问锁存器。

4. 发明申请

US20070164391A1 Trench isolation type semiconductor device and related method of manufacture 有权
标题翻译：沟槽隔离型半导体器件及相关制造方法
公开(公告)号：US20070164391A1
公开(公告)日：2007-07-19
申请号：US11650418
申请日：2007-01-08
申请人： Ki-seog Youn , Jong-hyon Ahn , Kwan-Jong Roh , Hye-Kyoung Lee
发明人： Ki-seog Youn , Jong-hyon Ahn , Kwan-Jong Roh , Hye-Kyoung Lee
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.
摘要翻译：公开了一种半导体器件及其制造方法。该装置包括：具有形成在所述半导体衬底中的角部的沟槽，形成在所述沟槽的内壁上并具有暴露所述半导体衬底的角部的上端部的第一氧化膜，形成在所述第一氧化物膜上的氮化物衬垫，与第一氧化物膜的上端接触形成的第二氧化物膜，暴露的角部和半导体衬底的上表面，形成在氮化物衬垫上以基本上填充沟槽的场绝缘膜，以及场保护膜形成为与第二氧化物膜接触并填充形成在场绝缘膜和第二氧化物膜之间的沟槽边缘凹陷。

5. 发明申请

US20060163669A1 Method of fabricating semiconductor device having silicide layer and semiconductor device fabricated thereby 审中-公开
公开(公告)号：US20060163669A1
公开(公告)日：2006-07-27
申请号：US11332150
申请日：2006-01-17
申请人： Ki-seog Youn , Jong-hyon Ahn , Su-gon Bae
发明人： Ki-seog Youn , Jong-hyon Ahn , Su-gon Bae
IPC分类号： H01L29/76
CPC分类号： H01L21/823443 , H01L21/823418
摘要： A method of fabricating a semiconductor device having a silicide layer and a semiconductor device fabricated by the method are provided. The method may involve providing a semiconductor substrate having an active region and a field region, and forming a plurality of gate patterns on each of the active region and the field region. The plurality of gate patterns may each have a sidewall spacer. The plurality of gate patterns on the field region include at least two adjacent gate patterns. The method may involve forming a silicide blocking layer pattern that masks a portion of the field region that exists between each of the adjacent gate patterns on the field region. The method may also involve forming a silicide layer on the active region and any of the plurality of the gate patterns that are not masked by the silicide blocking layer pattern.

6. 发明申请

US20060160351A1 Metal interconnect layer of semiconductor device and method for forming a metal interconnect layer 审中-公开
公开(公告)号：US20060160351A1
公开(公告)日：2006-07-20
申请号：US11385400
申请日：2006-03-21
申请人： Jong-hyon Ahn
发明人： Jong-hyon Ahn
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/31116 , H01L21/31138 , H01L21/31144 , H01L21/76804 , H01L21/76844 , H01L23/5283 , H01L23/53238 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： A metal interconnect layer of a semiconductor device, and a method for forming a metal interconnect layer of a semiconductor device are provided. The lower portion of a metal interconnect layer is wider than the upper portion of the metal interconnect layer. In another interconnect structure in accordance with the invention, the middle portion of the metal interconnect layer is wider than the upper and lower portions of the metal interconnect layer.

7. 发明申请

US20060128114A1 Trench isolation type semiconductor device and method of fabricating the same 有权
标题翻译：沟槽隔离型半导体器件及其制造方法
公开(公告)号：US20060128114A1
公开(公告)日：2006-06-15
申请号：US11301510
申请日：2005-12-13
申请人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
发明人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
摘要翻译：提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层，形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

8. 发明授权

US06555462B2 Semiconductor device having stress reducing laminate and method for manufacturing the same 失效
公开(公告)号：US06555462B2
公开(公告)日：2003-04-29
申请号：US09893456
申请日：2001-06-29
申请人： Jong-hyon Ahn , Chang-hun Lee
发明人： Jong-hyon Ahn , Chang-hun Lee
IPC分类号： H01L214763
CPC分类号： H01L23/5283 , H01L2924/0002 , H05K1/0271 , H05K3/4644 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has a stress reducing laminate. Grooves are formed on the surface of a material layer selected from a multilayer structure of the semiconductor device, for example, a conductive layer. The cross sections of the grooves are semicircular or semi-elliptic. The stress applied to the conductive layer having the grooves is divided into a vertical component and a horizontal component with respect to the surface of the conductive layer. Accordingly, the stress applied vertically to the conductive layer is reduced, making it is possible to prevent the conductive layer from cracking due to stress and to reduce the stress transmitted to material layers under the conductive layer.

9. 发明授权

US06335567B1 Semiconductor device having stress reducing laminate and method for manufacturing the same 失效
标题翻译：具有减压层压板的半导体装置及其制造方法
公开(公告)号：US06335567B1
公开(公告)日：2002-01-01
申请号：US09348830
申请日：1999-07-08
申请人： Jong-hyon Ahn , Chang-hun Lee
发明人： Jong-hyon Ahn , Chang-hun Lee
IPC分类号： H01L2348
CPC分类号： H01L23/5283 , H01L2924/0002 , H05K1/0271 , H05K3/4644 , Y10S438/926 , H01L2924/00
摘要： A semiconductor device has a stress reducing laminate. Grooves are formed on the surface of a material layer selected from a multilayer structure of the semiconductor device, for example, a conductive layer. The cross sections of the grooves are semicircular or semi-elliptic. The stress applied to the conductive layer having the grooves is divided into a vertical component and a horizontal component with respect to the surface of the conductive layer. Accordingly, the stress applied vertically to the conductive layer is reduced, making it is possible to prevent the conductive layer from cracking due to stress and to reduce the stress transmitted to material layers under the conductive layer.
摘要翻译：半导体器件具有应力降低层压板。在选自半导体器件的多层结构例如导电层的材料层的表面上形成沟槽。槽的横截面为半圆形或半椭圆形。施加到具有凹槽的导电层的应力相对于导电层的表面分成垂直分量和水平分量。因此，垂直于导电层施加的应力被降低，使得可以防止导电层由于应力而破裂，并且减小传递到导电层下面的材料层的应力。

10. 发明授权

US06300233B1 Method of making a fuse in a semiconductor device 有权
标题翻译：在半导体器件中制作保险丝的方法
公开(公告)号：US06300233B1
公开(公告)日：2001-10-09
申请号：US09714392
申请日：2000-11-16
申请人： Dong-Hun Lee , Jong-Hyon Ahn
发明人： Dong-Hun Lee , Jong-Hyon Ahn
IPC分类号： H01L2144
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a fuse of a semiconductor device and a method of forming a fuse of a semiconductor device. The method of the invention includes forming an underlying metal conductor on a semiconductor substrate, forming an insulating film over the underlying metal conductor, and selectively etching regions of the insulating film. One of the regions of the insulating film is etched to form a via contact region exposing the underlying metal conductor. A second region is etched to form a groove in the insulating film for the fuse metal. Metal is buried within the second etched region of the insulating film and the via contact region to respectively form a fuse metal pattern and a via contact metal layer. The fuse metal pattern can be formed from copper and/or tungsten.
摘要翻译：本发明提供一种半导体器件的熔丝和形成半导体器件的熔丝的方法。本发明的方法包括在半导体衬底上形成下面的金属导体，在下面的金属导体上形成绝缘膜，并选择性地蚀刻绝缘膜的区域。蚀刻绝缘膜的一个区域以形成暴露下面的金属导体的通孔接触区域。蚀刻第二区域以在用于熔丝金属的绝缘膜中形成凹槽。金属被埋在绝缘膜和通孔接触区域的第二蚀刻区域内，以分别形成熔丝金属图案和通孔接触金属层。熔丝金属图案可以由铜和/或钨形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式