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1. 发明授权

US08008177B2 Method for fabricating semiconductor device using a nickel salicide process 有权
标题翻译：使用镍硅化物工艺制造半导体器件的方法
公开(公告)号：US08008177B2
公开(公告)日：2011-08-30
申请号：US10621292
申请日：2003-07-17
申请人： Min-chul San , Ja-hum Ku , Chul-sung Kim , Kwan-jong Roh , Min-joo Kim
发明人： Min-chul San , Ja-hum Ku , Chul-sung Kim , Kwan-jong Roh , Min-joo Kim
IPC分类号： H01L21/28
CPC分类号： H01L29/6653 , H01L21/28518 , H01L29/665 , H01L29/6656 , H01L29/78
摘要： A method for fabricating a semiconductor device is provided using a nickel salicide process. The method includes forming a gate pattern and a source/drain region on a silicon substrate, forming a Ni-based metal layer for silicide on the silicon substrate where the gate pattern and the source/drain region are formed, and forming an N-rich titanium nitride layer on the Ni-based metal layer for silicide. Next, a thermal treatment is applied to the silicon substrate where the Ni-based metal layer for silicide and the N-rich titanium nitride layer are formed, thereby forming a nickel silicide on each of the gate pattern and the source/drain region. Then, the Ni-based metal layer for silicide and the N-rich titanium nitride layer are selectively removed to expose a top portion of a nickel silicide layer formed on the gate pattern and the source/drain region. Thus, as the N-rich titanium nitride layer is formed on the Ni-based metal layer for silicide, a silicide residue is prevented from forming a spacer and a field region formed of a field oxide layer.
摘要翻译：使用镍硅化物工艺提供半导体器件的制造方法。该方法包括在硅衬底上形成栅极图案和源极/漏极区域，在形成栅极图案和源极/漏极区域的硅衬底上形成用于硅化物的Ni基金属层，并形成富N 用于硅化物的Ni基金属层上的氮化钛层。接下来，对形成硅化物的Ni基金属层和形成有N的氮化钛层的硅基板进行热处理，从而在栅极图案和源极/漏极区域的每一个上形成硅化镍。然后，选择性地除去用于硅化物的Ni基金属层和富N极氮化钛层，以暴露形成在栅极图案和源极/漏极区上的硅化镍层的顶部。因此，由于在用于硅化物的Ni基金属层上形成富N的氮化钛层，因此防止了硅化物残留物形成间隔物和由场氧化物层形成的场区。

2. 发明授权

US07781322B2 Nickel alloy salicide transistor structure and method for manufacturing same 有权
标题翻译：镍合金硅化物晶体管结构及其制造方法
公开(公告)号：US07781322B2
公开(公告)日：2010-08-24
申请号：US10726638
申请日：2003-12-04
申请人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim
发明人： Ja-Hum Ku , Kwan-Jong Roh , Min-Chul Sun , Min-Joo Kim
IPC分类号： H01L21/3205
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28061 , H01L21/28518 , H01L29/4941 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： Provided are exemplary methods for forming a nickel silicide layer and semiconductor devices incorporating a nickel silicide layer that provides increased stability for subsequent processing at temperatures above 450° C. In particular, the nickel silicide layer is formed from a nickel alloy having a minor portion of an alloying metal, such as tantalum, and exhibits reduced agglomeration and retarded the phase transition between NiSi and NiSi2 to suppress increases in the sheet resistance and improve the utility for use with fine patterns. As formed, the nickel silicide layer includes both a lower layer consisting primarily of nickel and silicon and a thinner upper layer that incorporates the majority of the alloying metal.
摘要翻译：提供了用于形成硅化镍层的示例性方法和结合有硅化镍层的半导体器件，其为在450℃以上的温度下进行后续处理提供了更高的稳定性。特别地，硅化镍层由具有少部分合金化金属如钽，并且显示减少的结块并延缓NiSi和NiSi2之间的相变，以抑制薄层电阻的增加并提高使用精细图案的效用。如所形成的那样，硅化镍层包括主要由镍和硅组成的下层和掺入大部分合金金属的较薄的上层。

3. 发明申请

US20070187770A1 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US20070187770A1
公开(公告)日：2007-08-16
申请号：US11705164
申请日：2007-02-12
申请人： Jong-hyon Ahn , Jae-cheol Yoo , Ki-seog Youn , Kwan-jong Roh , Su-gon Bae , Ki-young Kim
发明人： Jong-hyon Ahn , Jae-cheol Yoo , Ki-seog Youn , Kwan-jong Roh , Su-gon Bae , Ki-young Kim
IPC分类号： H01L29/94 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/11 , H01L27/1104 , H01L29/7843
摘要： A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
摘要翻译：半导体集成电路器件可以包括半导体衬底，半导体衬底上的静态存储单元，下拉晶体管上的拉伸应力膜以及通过晶体管上的压应力膜。静态存储单元可以包括形成锁存器的多个上拉晶体管和下拉晶体管，并且多通道晶体管可用于访问锁存器。

4. 发明申请

US20070164391A1 Trench isolation type semiconductor device and related method of manufacture 有权
标题翻译：沟槽隔离型半导体器件及相关制造方法
公开(公告)号：US20070164391A1
公开(公告)日：2007-07-19
申请号：US11650418
申请日：2007-01-08
申请人： Ki-seog Youn , Jong-hyon Ahn , Kwan-Jong Roh , Hye-Kyoung Lee
发明人： Ki-seog Youn , Jong-hyon Ahn , Kwan-Jong Roh , Hye-Kyoung Lee
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A semiconductor device and related method of manufacture are disclosed. The device comprises; a trench having a corner portion formed in the semiconductor substrate, a first oxide film formed on an inner wall of the trench and having an upper end portion exposing the corner portion of the semiconductor substrate, a nitride liner formed on the first oxide film, a second oxide film formed in contact with the upper end of the first oxide film and on the exposed corner portion and an upper surface of the semiconductor substrate, a field insulating film formed on the nitride liner to substantially fill the trench, and a field protecting film formed in contact with the second oxide film and filling a trench edge recess formed between the field insulating film and the second oxide film.
摘要翻译：公开了一种半导体器件及其制造方法。该装置包括：具有形成在所述半导体衬底中的角部的沟槽，形成在所述沟槽的内壁上并具有暴露所述半导体衬底的角部的上端部的第一氧化膜，形成在所述第一氧化物膜上的氮化物衬垫，与第一氧化物膜的上端接触形成的第二氧化物膜，暴露的角部和半导体衬底的上表面，形成在氮化物衬垫上以基本上填充沟槽的场绝缘膜，以及场保护膜形成为与第二氧化物膜接触并填充形成在场绝缘膜和第二氧化物膜之间的沟槽边缘凹陷。

5. 发明授权

US07569483B2 Methods of forming metal silicide layers by annealing metal layers using inert heat transferring gases established in a convection apparatus 有权
标题翻译：通过在对流装置中建立的惰性热传递气体退火金属层来形成金属硅化物层的方法
公开(公告)号：US07569483B2
公开(公告)日：2009-08-04
申请号：US11199439
申请日：2005-08-08
申请人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
发明人： Sug-Woo Jung , Gil-Heyun Choi , Jong-Ho Yun , Kwan-Jong Roh , Eun-Ji Jung , Hyun-Su Kim
IPC分类号： H01L21/44
CPC分类号： H01L21/28518 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： Methods of forming metal silicide layers include a convection-based annealing step to convert a metal layer into a metal silicide layer. These methods may include forming a silicon layer on a substrate and forming a metal layer (e.g., nickel layer) in direct contact with the silicon layer. A step is then performed to convert at least a portion of the metal layer into a metal silicide layer. This conversion step is includes exposing the metal layer to an inert heat transferring gas (e.g., argon, nitrogen) in a convection or conduction apparatus.
摘要翻译：形成金属硅化物层的方法包括将金属层转化为金属硅化物层的基于对流的退火步骤。这些方法可以包括在衬底上形成硅层并形成与硅层直接接触的金属层（例如，镍层）。然后执行步骤以将至少一部分金属层转化为金属硅化物层。该转化步骤包括在对流或传导装置中将金属层暴露于惰性传热气体（例如氩气，氮气）。

6. 发明授权

US07932149B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07932149B2
公开(公告)日：2011-04-26
申请号：US12453676
申请日：2009-05-19
申请人： Jae-Hyun Park , Jeong-Uk Han , Jae-Min Yu , Young-Cheon Jeong , Sang-Hoon Park , Kwan-Jong Roh , Byeong-Cheol Lim , Yong-Seok Chung
发明人： Jae-Hyun Park , Jeong-Uk Han , Jae-Min Yu , Young-Cheon Jeong , Sang-Hoon Park , Kwan-Jong Roh , Byeong-Cheol Lim , Yong-Seok Chung
IPC分类号： H01L21/336
CPC分类号： H01L29/4234 , H01L27/11568 , H01L27/11573
摘要： In a method of manufacturing a semiconductor device, a tunnel insulation layer is formed on a substrate. A charge trapping layer is formed on the tunnel insulation layer. A protection layer pattern or a mold is formed on the charge trapping layer. Charge trapping layer patterns are formed on the tunnel insulation layer by etching the charge trapping layer using the protection layer pattern or the mold. The charge trapping layer patterns may be spaced apart from each other. Blocking layers are formed on the charge trapping layer patterns, respectively. A gate electrode is formed on the blocking layers and the tunnel insulation layer using the protection layer pattern or the mold.
摘要翻译：在制造半导体器件的方法中，在衬底上形成隧道绝缘层。在隧道绝缘层上形成电荷捕获层。在电荷捕获层上形成保护层图案或模具。通过使用保护层图案或模具蚀刻电荷捕获层，在隧道绝缘层上形成电荷俘获层图案。电荷捕获层图案可以彼此间隔开。阻挡层分别形成在电荷俘获层图案上。使用保护层图案或模具在阻挡层和隧道绝缘层上形成栅电极。

7. 发明授权

US07709340B2 Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07709340B2
公开(公告)日：2010-05-04
申请号：US11705164
申请日：2007-02-12
申请人： Jong-hyon Ahn , Jae-cheol Yoo , Ki-seog Youn , Kwan-jong Roh , Su-gon Bae , Ki-young Kim
发明人： Jong-hyon Ahn , Jae-cheol Yoo , Ki-seog Youn , Kwan-jong Roh , Su-gon Bae , Ki-young Kim
IPC分类号： H01L21/20
CPC分类号： H01L21/823807 , H01L21/823864 , H01L27/11 , H01L27/1104 , H01L29/7843
摘要： A semiconductor integrated circuit device may include a semiconductor substrate, a static memory cell on the semiconductor substrate, a tensile stress film on the pull-down transistors, and a compressive stress film on the pass transistors. The static memory cell may include multiple pull-up transistors and pull-down transistors, which form a latch, and multiple pass transistors may be used to access the latch.
摘要翻译：半导体集成电路器件可以包括半导体衬底，半导体衬底上的静态存储单元，下拉晶体管上的拉伸应力膜以及通过晶体管上的压应力膜。静态存储单元可以包括形成锁存器的多个上拉晶体管和下拉晶体管，并且多通道晶体管可用于访问锁存器。

8. 发明申请

US20060223296A1 Semiconductor device having self-aligned silicide layer and method thereof 审中-公开
标题翻译：具有自对准硅化物层的半导体器件及其方法
公开(公告)号：US20060223296A1
公开(公告)日：2006-10-05
申请号：US11180885
申请日：2005-07-13
申请人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sung-Kee Han , Min-Joo Kim , Kwan-Jong Roh
发明人： Min-Chul Sun , Ja-Hum Ku , Sug-Woo Jung , Sung-Kee Han , Min-Joo Kim , Kwan-Jong Roh
IPC分类号： H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28518 , H01L29/665
摘要： A semiconductor device having a self-aligned silicide layer and a method thereof are provided. The device includes a device isolation layer formed on the substrate to define an active region and a gate pattern crossing over the active region. A spacer insulating layer is formed on both sidewalls of the gate pattern. First and second salicide layers are formed on an upper portion of the gate pattern, and the first salicide layer is formed on the active region between the spacer insulating layer and the device isolation layer. The first and the second salicide layers on the gate pattern are alternately formed to be connected with each other. The first salicide layer is agglomeratedly formed on a narrow gate pattern, and the second salicide layer is formed within interrupted portions of the first salicide layer, thereby forming a patched salicide layer.
摘要翻译：提供了具有自对准硅化物层的半导体器件及其方法。该器件包括在衬底上形成的器件隔离层，以限定有源区和跨越有源区的栅极图案。在栅极图案的两个侧壁上形成间隔绝缘层。第一和第二自对准硅化物层形成在栅极图案的上部，并且第一自对准硅化物层形成在间隔绝缘层和器件隔离层之间的有源区上。栅极图案上的第一和第二自对准硅化物层交替地形成为彼此连接。第一自对准硅化物层在窄栅极图案上聚集形成，并且第二自对准硅化物层形成在第一自对准硅化物层的中断部分内，从而形成修补的自对准硅化物层。

9. 发明授权

US07005373B2 Method for forming a metal silicide layer in a semiconductor device 有权
标题翻译：在半导体器件中形成金属硅化物层的方法
公开(公告)号：US07005373B2
公开(公告)日：2006-02-28
申请号：US10790921
申请日：2004-03-02
申请人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
发明人： Eung-Joon Lee , In-Sun Park , Kwan-Jong Roh
IPC分类号： H01L21/4763
CPC分类号： H01L29/6653 , H01L21/823418 , H01L21/823468 , H01L21/823814 , H01L21/823835 , H01L21/823864 , H01L29/665
摘要： On first and second regions of a substrate are formed a first gate structure including a first gate electrode and a first spacer, and a second gate structure including a second gate electrode and a second spacer, respectively. The first and second spacers are removed to different depths such that side portions of the first and second gate electrodes have different exposed thicknesses. A metal silicide layer is formed on the first and second regions including the first and second gate structures. The metal silicide layer formed on the second gate electrode has a second thickness that is greater than a first thickness of the metal silicide layer formed on the first gate electrode. The spacers in the gate structures of resulting N type and P type MOS transistors are removed to different thicknesses, thereby minimizing deformation in the gate structures and also improving electrical characteristics and thermal stability of the gate electrodes.
摘要翻译：在衬底的第一和第二区域上分别形成包括第一栅极和第一间隔物的第一栅极结构，以及包括第二栅电极和第二间隔物的第二栅极结构。将第一和第二间隔物移除到不同的深度，使得第一和第二栅极的侧部具有不同的暴露厚度。在包括第一和第二栅极结构的第一和第二区域上形成金属硅化物层。形成在第二栅电极上的金属硅化物层具有大于形成在第一栅电极上的金属硅化物层的第一厚度的第二厚度。所得N型和P型MOS晶体管的栅极结构中的间隔物被去除到不同的厚度，从而最小化栅极结构中的变形，并且还改善栅电极的电特性和热稳定性。

10. 发明申请

US20050158996A1 Nickel salicide processes and methods of fabricating semiconductor devices using the same 审中-公开
标题翻译：镍硅化物工艺及使用其制造半导体器件的方法
公开(公告)号：US20050158996A1
公开(公告)日：2005-07-21
申请号：US10988848
申请日：2004-11-16
申请人： Min-Joo Kim , Ja-Hum Ku , Min-Chul Sun , Kwan-Jong Roh
发明人： Min-Joo Kim , Ja-Hum Ku , Min-Chul Sun , Kwan-Jong Roh
IPC分类号： H01L21/24 , H01L21/28 , H01L21/285 , H01L21/336 , H01L29/78 , H01L21/322
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518
摘要： A nickel salicide process includes preparing a substrate having a silicon region and an insulating region containing silicon. Nickel is deposited on the substrate, and the nickel is annealed at a first temperature of 300° C. to 380° C. to selectively form a mono-nickel mono-silicide layer on the silicon region and to leave an unreacted nickel layer on the insulating region. The unreacted nickel layer is selectively removed to expose the insulating region and to leave the mono-nickel mono-silicide layer on the silicon region. Subsequently, the mono-nickel mono-silicide layer is annealed at a second temperature which is higher than the first temperature to form a thermally stable mono-nickel mono-silicide layer and without a phase transition of the mono-nickel mono-silicide layer.
摘要翻译：镍硅化物工艺包括制备具有硅区和含硅绝缘区的衬底。镍沉积在衬底上，并且镍在300℃至380℃的第一温度下退火，以在硅区域上选择性地形成单镍单硅化物层，并在其上留下未反应的镍层绝缘区域。选择性地去除未反应的镍层以暴露绝缘区域并且在硅区域上留下单镍单硅化物层。随后，在高于第一温度的第二温度下对单镍单硅化物层进行退火，以形成热稳定的单镍一硅化物层，并且不存在单镍一硅化物层的相变。

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