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1. 发明授权

US07732280B2 Semiconductor device having offset spacer and method of forming the same 有权
标题翻译：具有偏移间隔物的半导体器件及其形成方法
公开(公告)号：US07732280B2
公开(公告)日：2010-06-08
申请号：US11905249
申请日：2007-09-28
申请人： Sung-Gun Kang
发明人： Sung-Gun Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/1083 , H01L21/26586 , H01L29/6656 , H01L29/6659
摘要： A method of forming a semiconductor device having an offset spacer may include forming a gate electrode on a semiconductor substrate. An etch stop layer including a nitride may be formed on the entire surface of the semiconductor substrate having the gate electrode. First spacers may be formed on the sidewalls of the gate electrode. The first spacers may be formed of a material layer having an etch selectivity with respect to the etch stop layer. The etch stop layer may be exposed on the semiconductor substrate on both sides of the gate electrode. Lightly-doped drain (LDD) regions may be formed in the semiconductor substrate using the gate electrode and the first spacers as an ion implantation mask. Second spacers may be formed on the first spacers. Accordingly, a semiconductor device having an offset spacer may be provided.
摘要翻译：形成具有偏移间隔物的半导体器件的方法可以包括在半导体衬底上形成栅电极。可以在具有栅电极的半导体衬底的整个表面上形成包括氮化物的蚀刻停止层。可以在栅电极的侧壁上形成第一间隔物。第一间隔物可以由相对于蚀刻停止层具有蚀刻选择性的材料层形成。蚀刻停止层可以在栅极两侧的半导体衬底上露出。可以使用栅电极和第一间隔物作为离子注入掩模在半导体衬底中形成轻掺杂漏极（LDD）区域。第二间隔物可以形成在第一间隔物上。因此，可以提供具有偏移间隔物的半导体器件。

2. 发明授权

US07358588B2 Trench isolation type semiconductor device which prevents a recess from being formed in a field region 有权
标题翻译：沟槽隔离型半导体器件防止在场区域中形成凹陷
公开(公告)号：US07358588B2
公开(公告)日：2008-04-15
申请号：US11301510
申请日：2005-12-13
申请人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
发明人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
IPC分类号： H01L29/00
CPC分类号： H01L21/76224
摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
摘要翻译：提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层，形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

3. 发明授权

US07288848B2 Overlay mark for measuring and correcting alignment errors 有权
标题翻译：用于测量和校正对准误差的叠加标记
公开(公告)号：US07288848B2
公开(公告)日：2007-10-30
申请号：US10997441
申请日：2004-11-23
申请人： Dong-Hun Lee , Jong-Hyon Ahn , Do-Yul Yoo , Sung-Gun Kang
发明人： Dong-Hun Lee , Jong-Hyon Ahn , Do-Yul Yoo , Sung-Gun Kang
IPC分类号： H01L23/544
CPC分类号： G03F7/70633 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , H01L2924/00
摘要： An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.
摘要翻译：覆盖标记包括形成在半导体衬底上的至少一个孔阵列和与孔阵列相邻的至少一个线性沟槽。孔阵列可以沿着预定方向形成为与线性沟槽相邻。当检测到在半导体衬底的预定部分形成的图形之间的对准误差时，重叠标记可以提供具有所需宽度和高电平的光的对比度，从而可以精确地检测和校正形成在半导体衬底上的图案的对准误差使用重叠标记。

4. 发明授权

US07846790B2 Method of fabricating semiconductor device having multiple gate dielectric layers and semiconductor device fabricated thereby 有权
标题翻译：制造具有多个栅介质层的半导体器件的方法和由此制造的半导体器件
公开(公告)号：US07846790B2
公开(公告)日：2010-12-07
申请号：US11877262
申请日：2007-10-23
申请人： Sung-Gun Kang , Kang-Soo Chu
发明人： Sung-Gun Kang , Kang-Soo Chu
IPC分类号： H01L21/8242
CPC分类号： H01L21/823462 , H01L27/105 , H01L27/108
摘要： A method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby, in which the method includes forming an isolation layer defining first and second active regions in a semiconductor substrate. A passivation layer is formed on the substrate having the isolation layer. A first patterning process is carried out that etches the passivation layer on the first active region to form a first opening exposing the first active region, and a first dielectric layer is formed in the exposed first active region. A second patterning process is carried out, which etches the passivation layer on the second active region to form a second opening exposing the second active region, and a second dielectric layer is formed in the exposed second active region.
摘要翻译：一种制造具有多个栅极电介质层的半导体器件的方法和由此制造的半导体器件，其中该方法包括在半导体衬底中形成限定第一和第二有源区的隔离层。在具有隔离层的基板上形成钝化层。执行第一图案化工艺，其蚀刻第一有源区上的钝化层以形成暴露第一有源区的第一开口，并且在暴露的第一有源区中形成第一介电层。执行第二图案化工艺，其蚀刻第二有源区上的钝化层以形成暴露第二有源区的第二开口，并且在暴露的第二有源区中形成第二介电层。

5. 发明申请

US20050110012A1 Overlay mark for measuring and correcting alignment errors 有权
标题翻译：用于测量和校正对准误差的叠加标记
公开(公告)号：US20050110012A1
公开(公告)日：2005-05-26
申请号：US10997441
申请日：2004-11-23
申请人： Dong-Hun Lee , Jong-Hyon Ahn , Do-Yul Yoo , Sung-Gun Kang
发明人： Dong-Hun Lee , Jong-Hyon Ahn , Do-Yul Yoo , Sung-Gun Kang
IPC分类号： H01L21/027 , G03F7/20 , H01L23/544 , H01L29/10
CPC分类号： G03F7/70633 , H01L23/544 , H01L2223/5442 , H01L2223/54453 , H01L2223/54466 , H01L2924/0002 , H01L2924/00
摘要： An overlay mark includes at least one hole array formed on a semiconductor substrate and at least one linear trench adjacent to the hole array. The hole array may be formed adjacent to the linear trench along a predetermined direction. When alignment errors among patterns formed at predetermined portion of the semiconductor substrate are detected, the overlay mark may provide a contrast of light with a desired width and a high level so that alignment errors of patterns formed on the semiconductor substrate may be accurately detected and corrected using the overlay mark.
摘要翻译：覆盖标记包括形成在半导体衬底上的至少一个孔阵列和与孔阵列相邻的至少一个线性沟槽。孔阵列可以沿着预定方向形成为与线性沟槽相邻。当检测到在半导体衬底的预定部分形成的图形之间的对准误差时，重叠标记可以提供具有所需宽度和高电平的光的对比度，从而可以精确地检测和校正形成在半导体衬底上的图案的对准误差使用重叠标记。

6. 发明授权

US07553606B2 Methods of forming patterns in semiconductor devices using photo resist patterns 有权
标题翻译：使用光刻胶图案在半导体器件中形成图案的方法
公开(公告)号：US07553606B2
公开(公告)日：2009-06-30
申请号：US11542988
申请日：2006-10-04
申请人： Sung-Gun Kang , Jin-Mo Kang , Jae-Ho Lee , Jun-Seop Lee
发明人： Sung-Gun Kang , Jin-Mo Kang , Jae-Ho Lee , Jun-Seop Lee
IPC分类号： G03C5/00
CPC分类号： H01L21/0277 , Y10S430/143
摘要： Disclosed is a method of forming patterns in semiconductor devices by using photo resist patterns. These methods comprise forming photo resist patterns on a substrate. Inferior patterns are selected among the photo resist patterns. The inferior patterns are eliminated or shrunken by irradiating the selected inferior patterns with an electron beam.
摘要翻译：公开了通过使用光刻胶图案在半导体器件中形成图案的方法。这些方法包括在基底上形成光刻胶图形。在光刻胶图案中选择下面的图案。通过用电子束照射所选择的下层图案来消除或缩小劣质图案。

7. 发明申请

US20070196769A1 Methods of forming patterns in semiconductor devices using photo resist patterns 有权
标题翻译：使用光刻胶图案在半导体器件中形成图案的方法
公开(公告)号：US20070196769A1
公开(公告)日：2007-08-23
申请号：US11542988
申请日：2006-10-04
申请人： Sung-Gun Kang , Jin-Mo Kang , Jae-Ho Lee , Jun-Seop Lee
发明人： Sung-Gun Kang , Jin-Mo Kang , Jae-Ho Lee , Jun-Seop Lee
IPC分类号： G06K9/00 , G03C5/00
CPC分类号： H01L21/0277 , Y10S430/143
摘要： Disclosed is a method of forming patterns in semiconductor devices by using photo resist patterns. These methods comprise forming photo resist patterns on a substrate. Inferior patterns are selected among the photo resist patterns. The inferior patterns are eliminated or shrunken by irradiating the selected inferior patterns with an electron beam.
摘要翻译：公开了通过使用光刻胶图案在半导体器件中形成图案的方法。这些方法包括在基底上形成光刻胶图形。在光刻胶图案中选择下面的图案。通过用电子束照射所选择的下层图案来消除或缩小劣质图案。

8. 发明申请

US20060128114A1 Trench isolation type semiconductor device and method of fabricating the same 有权
标题翻译：沟槽隔离型半导体器件及其制造方法
公开(公告)号：US20060128114A1
公开(公告)日：2006-06-15
申请号：US11301510
申请日：2005-12-13
申请人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
发明人： Ki-seog Youn , Jong-hyon Ahn , Deok-hyung Lee , Sung-gun Kang , Kong-soo Cheong
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A trench isolation type semiconductor device in which a recess is prevented from being formed in a field region and a method of fabricating the same are provided. The trench isolation type semiconductor device includes a semiconductor substrate defined by an active region and a field region, a trench formed in the field region, an oxide layer conformally formed along the inside of the trench, a liner layer conformally formed along the oxide layer, a field insulating layer formed inside the trench including the oxide layer and the liner layer, and a field protection layer formed on the field insulating layer so that a step difference does not occur on the semiconductor substrate.
摘要翻译：提供其中防止在场区域中形成凹部的沟槽隔离型半导体器件及其制造方法。沟槽隔离型半导体器件包括由有源区和场区定义的半导体衬底，在场区中形成的沟槽，沿着沟内部保形地形成的氧化物层，沿着氧化物层保形地形成的衬层，形成在包括氧化物层和衬垫层的沟槽内的场绝缘层，以及形成在场绝缘层上的场保护层，使得半导体衬底上不发生阶差。

9. 发明申请

US20080099856A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING MULTIPLE GATE DIELECTRIC LAYERS AND SEMICONDUCTOR DEVICE FABRICATED THEREBY 有权
标题翻译：制造具有多个栅极介电层的半导体器件的制造方法和其制造的半导体器件
公开(公告)号：US20080099856A1
公开(公告)日：2008-05-01
申请号：US11877262
申请日：2007-10-23
申请人： Sung-Gun Kang , Kang-Soo Chu
发明人： Sung-Gun Kang , Kang-Soo Chu
IPC分类号： H01L27/088 , H01L21/76
CPC分类号： H01L21/823462 , H01L27/105 , H01L27/108
摘要： A method of fabricating a semiconductor device having multiple gate dielectric layers and a semiconductor device fabricated thereby, in which the method includes forming an isolation layer defining first and second active regions in a semiconductor substrate. A passivation layer is formed on the substrate having the isolation layer. A first patterning process is carried out that etches the passivation layer on the first active region to form a first opening exposing the first active region, and a first dielectric layer is formed in the exposed first active region. A second patterning process is carried out, which etches the passivation layer on the second active region to form a second opening exposing the second active region, and a second dielectric layer is formed in the exposed second active region.
摘要翻译：一种制造具有多个栅极电介质层的半导体器件的方法和由此制造的半导体器件，其中该方法包括在半导体衬底中形成限定第一和第二有源区的隔离层。在具有隔离层的基板上形成钝化层。执行第一图案化工艺，其蚀刻第一有源区上的钝化层以形成暴露第一有源区的第一开口，并且在暴露的第一有源区中形成第一介电层。执行第二图案化工艺，其蚀刻第二有源区上的钝化层以形成暴露第二有源区的第二开口，并且在暴露的第二有源区中形成第二介电层。

10. 发明申请

US20050156199A1 Method of forming a CMOS device 审中-公开
标题翻译：形成CMOS器件的方法
公开(公告)号：US20050156199A1
公开(公告)日：2005-07-21
申请号：US11033207
申请日：2005-01-11
申请人： Young-Gun Ko , Sung-Gun Kang , Soo-Yong Lee , Jeong-Ho Shin
发明人： Young-Gun Ko , Sung-Gun Kang , Soo-Yong Lee , Jeong-Ho Shin
IPC分类号： H01L21/8238 , H01L29/73 , H01L23/48 , H01L29/74
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/823871
摘要： In a method of forming a CMOS device, first and second conductive structures are formed on a substrate. An insulation layer is formed on the substrate having the first and second conductive structures. The insulation layer is patterned to form an insulation layer pattern having a first portion on the first conductive structure and a second portion on the second conductive structure. The first portion has a compressive stress and functions as an etch stop layer. The second portion functions as an etch stop layer.
摘要翻译：在形成CMOS器件的方法中，在衬底上形成第一和第二导电结构。在具有第一和第二导电结构的基板上形成绝缘层。对绝缘层进行构图以形成绝缘层图案，该绝缘层图案具有第一导电结构上的第一部分和第二导电结构上的第二部分。第一部分具有压缩应力并用作蚀刻停止层。第二部分用作蚀刻停止层。

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