专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06735106B2 Accelerated fatigue testing 有权
标题翻译：加速疲劳试验
公开(公告)号：US06735106B2
公开(公告)日：2004-05-11
申请号：US10190102
申请日：2002-07-02
申请人： Juergen T. Rickes , Hugh P. McAdams , James W. Grace , John Y. Fong , Ralph H. Lanham
发明人： Juergen T. Rickes , Hugh P. McAdams , James W. Grace , John Y. Fong , Ralph H. Lanham
IPC分类号： G11C1122
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： A memory such as a FeRAM implements accelerated fatigue operations that simultaneously change the storage state of large numbers of memory cells and can be rapidly repeated. In one embodiment, the FeRAM includes multiple segments with plate lines in each segment being isolated from plate lines in other segments. A first fatigue operation uses standard read/write decoding for word lines but simultaneously activates all segments. A second fatigue operation activates all segments and all plate lines and exercises one row of memory cells in each plate line group. A third fatigue operation is similar to the second but cycles through rows in the plate line groups so that a number of repetitions of the third fatigue operation equally fatigue every FeRAM cell.
摘要翻译：诸如FeRAM的存储器实现加速疲劳操作，其同时改变大量存储器单元的存储状态并且可以快速重复。在一个实施例中，FeRAM包括多个段，每个段中的板线与其它段中的板线隔离。第一次疲劳操作使用字线的标准读/写解码，但同时激活所有段。第二次疲劳操作激活所有的段和所有的板条，并在每个板组组中锻炼一行记忆单元。第三个疲劳操作类似于第二个但是在板组组中的行循环，使得第三疲劳操作的重复次数对于每个FeRAM单元同样疲劳。

2. 发明授权

US07301795B2 Accelerated low power fatigue testing of FRAM 有权
标题翻译： FRAM加速低功耗疲劳试验
公开(公告)号：US07301795B2
公开(公告)日：2007-11-27
申请号：US11260987
申请日：2005-10-28
申请人： John Y. Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Kumar Madan , Jarrod Eliason
发明人： John Y. Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Kumar Madan , Jarrod Eliason
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译：系统和方法使铁电存储器件疲劳。在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

3. 发明授权

US07630258B2 Decoder based set associative repair cache systems and methods 有权
标题翻译：基于解码器的集合关联修复缓存系统和方法
公开(公告)号：US07630258B2
公开(公告)日：2009-12-08
申请号：US11230438
申请日：2005-09-20
申请人： John Y. Fong
发明人： John Y. Fong
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G11C29/72 , G11C29/808 , G11C29/812
摘要： The present invention facilitates memory devices and operation thereof by employing a repair cache system 600 to correct or repair identified faulty memory locations. The repair cache system 600 includes a decoder that selects local repair location addresses from repair sets 610 according to a repair region address 604. Comparators 616 compare the selected local repair location addresses with a local repair address 606 to identify a match. Repair register banks 622 that comprise a plurality of repair registers are selected if an associated comparator 606 identifies a match. Then, a register within the associated register bank is selected according the repair region address 604 for read/write access. If a match is not identified, a memory location from a main memory 630 is selected for read/write access.
摘要翻译：本发明通过采用修理高速缓存系统600来校正或修复所识别的故障存储器位置来便利存储器件及其操作。修理缓存系统600包括根据修复区域地址604从修复集610中选择本地修复位置地址的解码器。比较器616将所选择的本地修复位置地址与本地修复地址606进行比较，以识别匹配。如果相关联的比较器606识别匹配，则选择包括多个修复寄存器的修复寄存器组622。然后，根据修复区域地址604选择相关联的寄存器组内的寄存器以进行读/写访问。如果未识别出匹配，则选择来自主存储器630的存储器位置用于读/写访问。

4. 发明授权

US06590799B1 On-chip charge distribution measurement circuit 失效
标题翻译：片上电荷分布测量电路
公开(公告)号：US06590799B1
公开(公告)日：2003-07-08
申请号：US10158279
申请日：2002-05-29
申请人： Juergen T. Rickes , Hugh P. McAdams , James W. Grace , John Y. Fong , Ralph H. Lanham
发明人： Juergen T. Rickes , Hugh P. McAdams , James W. Grace , John Y. Fong , Ralph H. Lanham
IPC分类号： G11C1122
CPC分类号： G11C29/028 , G11C11/22 , G11C29/12005 , G11C29/50 , G11C29/50016 , G11C2029/2602 , G11C2029/5002
摘要： A method and circuit for measuring a charge distribution for readout from FeRAM cells is fast enough for an on-chip defect detection and parameter adjustment. A comparator-type sense amplifier and a reference voltage generator measure a bit line charge or voltage using one readout of charge from an FeRAM cell and comparisons of the resulting bit line voltage to a series of reference voltages. A series of result signals from the sense amplifier indicates when the bit line voltage is approximately equal to the reference voltage. The results signals can be output for analysis and/or used internally for defect detection or setting of operating parameters such as a reference used during read operations.
摘要翻译：用于测量从FeRAM单元读出的电荷分布的方法和电路足够快以进行片上缺陷检测和参数调整。比较器型读出放大器和参考电压发生器使用来自FeRAM单元的一次读出电荷测量位线电荷或电压，并将所得位线电压与一系列参考电压进行比较。来自读出放大器的一系列结果信号指示位线电压何时近似等于参考电压。结果信号可以输出用于分析和/或内部使用，用于缺陷检测或设置操作参数，例如在读取操作期间使用的参考。

5. 发明授权

US06809954B1 Circuit and method for reducing access transistor gate oxide stress 有权
标题翻译：减少存取晶体管栅极氧化应力的电路和方法
公开(公告)号：US06809954B1
公开(公告)日：2004-10-26
申请号：US10614299
申请日：2003-07-02
申请人： Sudhir K. Madan , Hugh McAdams , John Y. Fong
发明人： Sudhir K. Madan , Hugh McAdams , John Y. Fong
IPC分类号： G11C1122
CPC分类号： G11C8/08 , G11C11/22
摘要： A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first 106 and a second 110 control terminal and a pass transistor 102. The pass transistor has a control gate coupled to the first control terminal. The memory circuit includes a drive circuit 900 having an output terminal 912 coupled to the second control terminal. The drive circuit is arranged to produce a control signal PL having a rise time and a fall time, wherein the fall time is greater than the rise time.
摘要翻译：公开了一种用于减少栅极氧化应力的存储电路和方法。电路包括用于存储数据的存储单元。存储单元具有第一106和第二110控制端和传输晶体管102.传输晶体管具有耦合到第一控制端的控制栅。存储器电路包括具有耦合到第二控制端子的输出端子912的驱动电路900。驱动电路被配置为产生具有上升时间和下降时间的控制信号PL，其中下降时间大于上升时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式