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1. 发明授权

US08296628B2 Data path read/write sequencing for reduced power consumption 有权
标题翻译：数据路径读/写排序，降低功耗
公开(公告)号：US08296628B2
公开(公告)日：2012-10-23
申请号：US12699357
申请日：2010-02-03
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： G11C29/00
CPC分类号： G06F11/1048 , G11C11/22
摘要： A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided.
摘要翻译：一种固态存储器，例如具有复用内部数据总线的铁电随机存取存储器（FeRAM），并减少数据传输的功耗。存储器以具有纠错编码（ECC）的多字节数据字的形式存储数据。在页面模式读/写操作中，存储在所选行的存储器单元中的数据状态由布置在第一和第二存储体中的读出放大器感测，其与第一组和第二组相关联。与第一组列相关联并且包含ECC值的第一组读出放大器被耦合到内部总线，随后将与第二组列相关联的第二组读出放大器耦合到内部总线。然后将内部总线置于三态，随后内部数据总线被驱动，数据被写入同一行的第二组列，该数据被锁存在第二组读出放大器中。然后，内部总线被驱动，数据被写入行中的第一组列，并被锁存在第一组读出放大器中。在第二组列中的数据从读取到写入操作不改变的情况下，避免了切换内部总线所需的功耗。

2. 发明申请

US20110231736A1 Low-Power Redundancy for Non-Volatile Memory 有权
标题翻译：非易失性存储器的低功耗冗余
公开(公告)号：US20110231736A1
公开(公告)日：2011-09-22
申请号：US12958724
申请日：2010-12-02
申请人： David J. Toops , Sudhir K. Madan , Suresh Balasubramanian
发明人： David J. Toops , Sudhir K. Madan , Suresh Balasubramanian
IPC分类号： G11C7/22 , H03M13/05 , G06F11/10
CPC分类号： G11C29/84 , G06F11/1016 , G11C7/02 , G11C11/22 , G11C29/789 , G11C29/83
摘要： A static RAM redundancy memory for use in combination with a non-volatile memory array, such as ferroelectric RAM (FRAM), in which the power consumption of the SRAM redundancy memory is reduced. Each word of the redundancy memory includes data bit cells for storing addresses of memory cells in the FRAM array to be replaced by redundant elements, and also enable bits indicating whether redundancy is enabled for those addresses. A logical combination of the enable bits in a given word determines whether the data bit cells in that word are powered-up. As a result, the power consumption of the redundancy memory is reduced to the extent that redundancy is not enabled for segments of the FRAM array.
摘要翻译：用于与诸如铁电RAM（FRAM）的非易失性存储器阵列组合使用的静态RAM冗余存储器，其中减少了SRAM冗余存储器的功耗。冗余存储器的每个字包括数据位单元，用于存储要由冗余元件代替的FRAM阵列中的存储器单元的地址，并且还使能指示是否为这些地址启用冗余的位。给定字中的使能位的逻辑组合确定该字中的数据位单元是否通电。结果，冗余存储器的功耗被降低到对FRAM阵列的段的冗余不起作用的程度。

3. 发明申请

US20110035644A1 Data Path Read/Write Sequencing for Reduced Power Consumption 有权
标题翻译：数据路径读/写排序，降低功耗
公开(公告)号：US20110035644A1
公开(公告)日：2011-02-10
申请号：US12699357
申请日：2010-02-03
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： G06F11/08
CPC分类号： G06F11/1048 , G11C11/22
摘要： A solid-state memory such as a ferroelectric random access memory (FeRAM) with multiplexed internal data bus and reduced power consumption on data transfer. The memory stores data in the form of multi-byte data words with error correction coding (ECC). In a page mode read/write operation, data states stored in memory cells of the selected row are sensed by sense amplifiers arranged in first and second banks, which are associated with first and second groups of columns. The first bank of sense amplifiers, associated with the first group of columns and containing the ECC value, are coupled to to the internal bus, followed by coupling the second bank of sense amplifiers associated with the second group of columns to the internal bus. The internal bus is then placed in tri-state, following which the internal data bus is driven with data to be written into the second group of columns in that same row, that data latched into the second bank of sense amplifiers. The internal bus is then driven with the data to be written to the first group of columns in the row, and latched into the first bank of sense amplifiers. To the extent that the data in the second group of columns does not change from the read to write operations, power consumption otherwise necessary for switching the internal bus is avoided.
摘要翻译：一种固态存储器，例如具有复用内部数据总线的铁电随机存取存储器（FeRAM），并减少数据传输的功耗。存储器以具有纠错编码（ECC）的多字节数据字的形式存储数据。在页面模式读/写操作中，存储在所选行的存储器单元中的数据状态由布置在第一和第二存储体中的读出放大器感测，其与第一组和第二组相关联。与第一组列相关联并且包含ECC值的第一组读出放大器被耦合到内部总线，随后将与第二组列相关联的第二组读出放大器耦合到内部总线。然后将内部总线置于三态，随后内部数据总线被驱动，数据被写入同一行的第二组列，该数据被锁存在第二组读出放大器中。然后，内部总线被驱动，数据被写入行中的第一组列，并被锁存在第一组读出放大器中。在第二组列中的数据从读取到写入操作不改变的情况下，避免了切换内部总线所需的功耗。

4. 发明申请

US20090154220A1 PLATELINE DRIVER FOR A FERROELECTRIC MEMORY 有权
标题翻译：用于电磁记忆体的定位驱动器
公开(公告)号：US20090154220A1
公开(公告)日：2009-06-18
申请号：US11955861
申请日：2007-12-13
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： One embodiment relates to a ferroelectric memory device. The ferroelectric memory device includes a memory array comprising one or more ferroelectric memory cells that are arranged in a number of plateline groups. The memory device also includes a plateline driver configured to boost a plateline voltage above a supply voltage within the plateline driver, and provide the boosted plateline voltage along platelines associated with the plateline driver. Other methods and systems are also disclosed.
摘要翻译：一个实施例涉及铁电存储器件。铁电存储器件包括存储器阵列，该存储器阵列包括布置在多个板阵组中的一个或多个铁电存储器单元。该存储装置还包括一个平板驱动器，其被配置为将板极电压升高到该平板驱动器内的电源电压以上，并且沿着与该平板驱动器相关联的平板电路提供升高的平行线电压。还公开了其它方法和系统。

5. 发明授权

US07230868B2 Stable source-coupled sense amplifier 有权
标题翻译：稳定的源极耦合读出放大器
公开(公告)号：US07230868B2
公开(公告)日：2007-06-12
申请号：US11191709
申请日：2005-07-28
申请人： Sudhir K. Madan , Bryan Sheffield
发明人： Sudhir K. Madan , Bryan Sheffield
IPC分类号： G11C7/06
CPC分类号： G11C7/065 , G11C11/22
摘要： An amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706, 708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726), and third pull down transistor between the first and second input terminals. The control gates of the first, second and third pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.
摘要翻译：放大器电路包括放大器部分（700），均衡部分（770）和激活部分（720）。放大器部分的P沟道晶体管（702,704）耦合到电源端子（802）。放大器部分的N沟道晶体管（706,708）分别耦合在P沟道晶体管和第一和第二输入端（760,762）之间。在激活部分中，第一和第二下拉晶体管（722,724）分别耦合在第一和第二输入端之间，第二电源端（726）和第三和第二输入端之间的第三下拉晶体管。第一，第二和第三下拉晶体管的控制栅彼此耦合。在操作中，施加到第一和第二输入端的电压信号被N沟道晶体管放大。然后施加控制信号以将第一和第二输入端耦合到电源电压。

6. 发明授权

US06757206B2 Sense amplifier with override write circuitry 有权
标题翻译：带超声写入电路的感应放大器
公开(公告)号：US06757206B2
公开(公告)日：2004-06-29
申请号：US10245081
申请日：2002-09-17
申请人： Hugh P. McAdams , Juergen Rickes , Sudhir K. Madan
发明人： Hugh P. McAdams , Juergen Rickes , Sudhir K. Madan
IPC分类号： G11C702
CPC分类号： G11C11/22 , G11C7/06 , G11C7/1048 , G11C2207/002 , G11C2207/2281 , G11C2207/229
摘要： Methods and apparatus are disclosed for selectively coupling sense amps with local IO lines in memory devices, comprising first and second selection systems operable to selectively couple a sense amp terminal with a local IO line. A first selection system is coupled with a local IO line and a sense amp, providing selective coupling thereof a second time period after the sense amp is enabled. A second selection system is coupled with the local IO line and the sense amp, which couples the local IO line with the sense amp a first time period before the sense amp is enabled during a write operation, wherein the first time period may be zero.
摘要翻译：公开了用于选择性地将感测放大器与存储器件中的本地IO线耦合的方法和装置，包括可操作以选择性地将感测放大器端子与本地IO线耦合的第一和第二选择系统。第一选择系统与本地IO线路和感测放大器耦合，在感测放大器被使能之后的第二时间段提供其选择性耦合。第二选择系统与本地IO线和感测放大器耦合，其在写操作期间在感测放大器被启用之前的第一时间周期将本地IO线耦合到感测放大器，其中第一时间段可以为零。

7. 发明授权

US5629228A Method of making stacked DRAM capacitor structure by using a conformal conductor 失效
标题翻译：通过使用共形导体制作堆叠的DRAM电容器结构的方法
公开(公告)号：US5629228A
公开(公告)日：1997-05-13
申请号：US482136
申请日：1995-06-07
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L28/87
摘要： A method of forming a microelectronic device is described comprising the steps of providing a substrate, forming a conductive region on the substrate, and forming an insulating layer on said conductive region and said substrate. The method further comprises the steps of forming a spacer layer on said insulating layer, removing selective portions of said spacer layer and said insulating layer to expose a selective area of said conductive region thereby forming a storage node contact window, and forming a first conductive layer on said spacer layer and within said storage node contact window wherein said first conductive layer is in electrical communication with said conductive region. A storage electrode is formed by removing selective portions of said first conductive layer, removing said spacer layer thereby exposing a bottom surface area of said first conductive layer, conformably depositing a second conductive layer encompassing and in electrical communication with said first conductive layer and overlying said insulating layer, and etching a portion of said second conductive layer thereby isolating said second conductive layer from surrounding circuit elements. The capacitor is completed by forming a dielectric layer over said storage electrode and forming a third conductive layer which acts as a plate electrode capacitively-coupled to said storage electrode through said dielectric layer. Other devices, systems and methods are also disclosed.
摘要翻译：描述形成微电子器件的方法包括以下步骤：提供衬底，在衬底上形成导电区域，以及在所述导电区域和所述衬底上形成绝缘层。该方法还包括以下步骤：在所述绝缘层上形成间隔层，去除所述间隔层和所述绝缘层的选择性部分，以暴露所述导电区域的选择区域，从而形成存储节点接触窗口，以及形成第一导电层在所述间隔层和所述存储节点接触窗口内，其中所述第一导电层与所述导电区域电连通。通过去除所述第一导电层的选择性部分来形成存储电极，去除所述间隔层，从而暴露所述第一导电层的底表面区域，从而顺应地沉积包围并与所述第一导电层电连通的第二导电层，并覆盖所述绝缘层，并且蚀刻所述第二导电层的一部分，从而将所述第二导电层与周围的电路元件隔离。通过在所述存储电极上形成电介质层并形成第三导电层来完成电容器，该第三导电层用作通过所述介电层电容耦合到所述存储电极的平板电极。还公开了其他装置，系统和方法。

8. 发明授权

US4994873A Local interconnect for stacked polysilicon device 失效
标题翻译：堆叠多晶硅器件的局部互连
公开(公告)号：US4994873A
公开(公告)日：1991-02-19
申请号：US456712
申请日：1989-12-26
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8244
CPC分类号： H01L21/8221 , H01L21/76895 , H01L27/11 , Y10S257/903
摘要： A semiconductor device is formed in an active region of a substrate. The device has first and second polysilicon strips which are aligned. The first polysilicon strip is somewhat wider than the second. A contact is formed between the second polysilicon strip and a region in the active region. The contact is ensured of not shorting to the first polysilicon strip by the use of an extra sidewall spacer. One sidewall is already present but is etched down to expose the second polysilicon strip. The etching down of the one sidewall spacer may also expose a corner of the first polysilicon strip. The extra sidewall spacer covers the potentially exposed corner. The first polysilicon strip can also have a neck portion protruding toward the second polysilicon strip and aligned with the second polysilicon strip. This further improves the margin by which the contact will avoid the corner of the first polysilicon strip.
摘要翻译：半导体器件形成在衬底的有源区中。该器件具有对准的第一和第二多晶硅条。第一个多晶硅条有些宽于第二个。在第二多晶硅条和有源区中的区域之间形成接触。通过使用额外的侧壁间隔件确保接触不与第一多晶硅条短路。一个侧壁已经存在，但被蚀刻以露出第二多晶硅条。一个侧壁间隔物的蚀刻也可能暴露第一多晶硅条的拐角。额外的侧壁间隔物覆盖潜在的暴露角。第一多晶硅条还可具有向第二多晶硅条突出并与第二多晶硅条对准的颈部。这进一步提高了触点避免第一多晶硅条的拐角的余量。

9. 发明申请

US20130093245A1 METHOD TO MAINTAIN POWER SUPPLY VOLTAGE DURING BROWNOUT 有权
标题翻译：在BROWNOUT中保持电源电压的方法
公开(公告)号：US20130093245A1
公开(公告)日：2013-04-18
申请号：US13312388
申请日：2011-12-06
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： H02J9/00
CPC分类号： G11C5/145 , G11C11/22 , Y10T307/62
摘要： A method of maintaining a power supply voltage during a brownout is disclosed. The method includes the step of storing a charge in a charge reservoir (608) and storing a charge on a power supply capacitor (832). A charge from the charge reservoir is applied to the power supply capacitor in response to a power supply fail signal (BROWNOUT).
摘要翻译：公开了一种在掉电期间维持电源电压的方法。该方法包括将电荷存储在电荷贮存器（608）中并将电荷存储在电源电容器（832）上的步骤。响应于电源故障信号（BROWNOUT），将电荷储存器的电荷施加到电源电容器。

10. 发明申请

US20130051109A1 Method of reading a ferroelectric memory cell 有权
标题翻译：读取铁电存储单元的方法
公开(公告)号：US20130051109A1
公开(公告)日：2013-02-28
申请号：US13199275
申请日：2011-08-23
申请人： Sudhir K. Madan
发明人： Sudhir K. Madan
IPC分类号： G11C11/22 , G11C7/02 , G11C7/06 , G11C7/12
CPC分类号： G11C7/02 , G11C7/12 , G11C7/18 , G11C11/2273
摘要： A method of reading a memory cell is disclosed. The method includes the step of connecting (708) a reference voltage generator (600) to a first bitline (/BL). The first bitline is charged to a reference voltage (VREF) from the reference voltage generator. The reference voltage generator is disconnected (RFWL_A/B low at t4, FIG. 10B) from the first bitline. A signal voltage (PL high at t4, FIG. 10B) from the memory cell is applied to a second bitline (BL) after the step of disconnecting. A difference voltage between the first and second bitlines is amplified (SAEN high at t7, FIGS. 8A and 10B).
摘要翻译：公开了一种读取存储单元的方法。该方法包括将参考电压发生器（600）连接（708）到第一位线（/ BL）的步骤。第一位线从参考电压发生器充电到参考电压（VREF）。参考电压发生器从第一位线断开（在t4，图10B的RFWL_A / B为低电平）。在断开步骤之后，将来自存储单元的信号电压（在t4处的PL高，图10B中的高电平）施加到第二位线（BL）。第一位和第二位线之间的差分电压被放大（在图7和图10B的t7为SAEN为高）。

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