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1. 发明授权

US07301795B2 Accelerated low power fatigue testing of FRAM 有权
标题翻译： FRAM加速低功耗疲劳试验
公开(公告)号：US07301795B2
公开(公告)日：2007-11-27
申请号：US11260987
申请日：2005-10-28
申请人： John Y. Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Kumar Madan , Jarrod Eliason
发明人： John Y. Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Kumar Madan , Jarrod Eliason
IPC分类号： G11C11/22
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译：系统和方法使铁电存储器件疲劳。在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

2. 发明授权

US07133304B2 Method and apparatus to reduce storage node disturbance in ferroelectric memory 有权
标题翻译：减少铁电存储器节点干扰的方法和装置
公开(公告)号：US07133304B2
公开(公告)日：2006-11-07
申请号：US10805809
申请日：2004-03-22
申请人： Sudhir Kumar Madan , Sung-Wei Lin , Hugh P. McAdams , Anand Seshadri , Jarrod Eliason
发明人： Sudhir Kumar Madan , Sung-Wei Lin , Hugh P. McAdams , Anand Seshadri , Jarrod Eliason
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要翻译：提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

3. 发明申请

US20050207201A1 Method and apparatus to reduce storage node disturbance in ferroelectric memory 有权
标题翻译：减少铁电存储器节点干扰的方法和装置
公开(公告)号：US20050207201A1
公开(公告)日：2005-09-22
申请号：US10805809
申请日：2004-03-22
申请人： Sudhir Madan , Sung-Wei Lin , Hugh McAdams , Anand Seshadri , Jarrod Eliason
发明人： Sudhir Madan , Sung-Wei Lin , Hugh McAdams , Anand Seshadri , Jarrod Eliason
IPC分类号： G11C11/22 , G11C11/24
CPC分类号： G11C11/22
摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.
摘要翻译：提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

4. 发明申请

US20060107095A1 Accelerated low power fatigue testing of fram 有权
标题翻译：框架加速低功率疲劳试验
公开(公告)号：US20060107095A1
公开(公告)日：2006-05-18
申请号：US11260987
申请日：2005-10-28
申请人： John Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Madan , Jarrod Eliason
发明人： John Fong , Anand Seshadri , Sung-Wei Lin , Sudhir Madan , Jarrod Eliason
IPC分类号： G06F11/00
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002
摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.
摘要翻译：系统和方法使铁电存储器件疲劳。在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

5. 发明申请

US20060140017A1 Ferroelectric memory reference generator systems using staging capacitors 有权
标题翻译：铁电存储器参考发电机系统采用分级电容器
公开(公告)号：US20060140017A1
公开(公告)日：2006-06-29
申请号：US11100013
申请日：2005-04-06
申请人： Anand Seshadri , Jarrod Eliason , Sudhir Madan
发明人： Anand Seshadri , Jarrod Eliason , Sudhir Madan
IPC分类号： G11C11/22 , G11C5/14
CPC分类号： G11C11/22
摘要： Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S1) couples the staging capacitance (Cs) to the precharged primary capacitance (130) and then isolates the precharged staging capacitance (Cs) from the primary capacitance (130), and the second switching device (S2, S3) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (130), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.
摘要翻译：参考发生器系统（108,130）和方法（200）被提供用于为铁电存储器件（102）中的存储器存取操作提供位线参考电压。参考发生器系统（108,130）包括初级电容（130），对初级电容充电的预充电系统（132）以及具有多个与相应的电压相关联的多个局部参考电路（108a）的参考系统（108）单独地包括分级电容（Cs）的阵列列，耦合在所述分级电容和所述初级电容（130）之间的第一开关器件（S1）以及耦合在所述分级电容之间的第二开关器件（S 2，S 3）（Cs）和相应阵列列的位线。第一开关器件（S1）将分级电容（Cs）耦合到预充电的初级电容（130），然后将预充电的分级电容（Cs）与主电容（130）隔离，并且第二开关器件（S2， S 3）将分级电容（Cs）与位线分离，而分级电容Cs耦合到初级电容（130），然后将预充电分级电容（Cs）耦合到位线，以在位线期间向位线提供参考电压内存访问操作。

6. 发明申请

US20070038805A1 High granularity redundancy for ferroelectric memories 审中-公开
标题翻译：铁电存储器的高粒度冗余
公开(公告)号：US20070038805A1
公开(公告)日：2007-02-15
申请号：US11200390
申请日：2005-08-09
申请人： Jarrod Eliason , Sudhir Madan , Sung-Wei Lin , Hugh McAdams
发明人： Jarrod Eliason , Sudhir Madan , Sung-Wei Lin , Hugh McAdams
IPC分类号： G06F12/00
CPC分类号： G11C29/848 , G11C11/22 , G11C29/816
摘要： A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.
摘要翻译：公开了处理或处理有缺陷的“晶粒”或非易失性铁电存储器阵列的部分的方案。在一个示例中，存储器的颗粒小于高和小于行宽的列。当修复编程组发现部分的地址对应于失败的行地址和故障列地址时，对存储器部分执行替换操作。

7. 发明授权

US06650158B2 Ferroelectric non-volatile logic elements 有权
公开(公告)号：US06650158B2
公开(公告)日：2003-11-18
申请号：US10076058
申请日：2002-02-12
申请人： Jarrod Eliason
发明人： Jarrod Eliason
IPC分类号： H03K3289
CPC分类号： G11C11/22 , G11C19/005 , H03K3/356008 , H03K3/45
摘要： Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.

8. 发明授权

US6141237A Ferroelectric non-volatile latch circuits 有权
标题翻译：铁电非易失性锁存电路
公开(公告)号：US6141237A
公开(公告)日：2000-10-31
申请号：US351563
申请日：1999-07-12
申请人： Jarrod Eliason , William F. Kraus
发明人： Jarrod Eliason , William F. Kraus
IPC分类号： G11C11/22 , H01L21/8246 , H01L27/105 , H03K3/356
CPC分类号： G11C11/22
摘要： A non-volatile ferroelectric latch includes a sense amplifier having at least one input/output coupled to a bit-line node, a ferroelectric storage capacitor coupled between a plate-line node and the bit-line node, and a load element coupled to the bit-line node. The sense amplifier further includes a second input/output coupled to a second bit-line node and the latch further includes a second ferroelectric storage capacitor coupled between a second plate-line node and the second bit-sine node, and a second load element coupled to the second bit-line node. The load element includes a dynamic, switched ferroelectric capacitor a static, nonswitched ferroelectric capacitor, a linear capacitor, or even a resistive load.
摘要翻译：非挥发性铁电锁存器包括读出放大器，其具有耦合到位线节点的至少一个输入/输出，耦合在板状线节点和位线节点之间的铁电存储电容器以及耦合到该位线线路节点的负载元件位线节点。感测放大器还包括耦合到第二位线节点的第二输入/输出，并且锁存器还包括耦合在第二板状线节点和第二位正弦节点之间的第二铁电存储电容器，以及耦合到第二负载元件的第二负载元件到第二位线节点。负载元件包括动态的，开关的铁电电容器，静态的，非开关的铁电电容器，线性电容器或甚至电阻负载。

9. 发明授权

US11372620B1 Voice monitoring system and method 有权
公开(公告)号：US11372620B1
公开(公告)日：2022-06-28
申请号：US17399459
申请日：2021-08-11
申请人： Jarrod Eliason
发明人： Jarrod Eliason
IPC分类号： G06F3/16 , G06F1/16 , G06Q10/10 , G06F3/0488 , G06F3/01
摘要： An exemplary voice monitoring system includes a wearable voice monitor and an auxiliary device such as a smart phone. The wearable monitor incorporates a wake-on-sound microphone, a vibration motor, and a microcontroller within a small, discreet enclosure. The enclosure can be hung from a necklace chain or affixed to clothing, like a piece of jewelry. The jewelry appearance is enhanced by a removable decorative piece. The microcontroller wakes up in response to a wake signal from the microphone when a voice sound of a wearer is detected. The microcontroller initiates measurements to determine if the voice sound meets preconfigured criteria and activates the vibration motor to alert the wearer. Sound criteria resulting in vibratory alerts are contained in a user-specific schedule tailored according to time of day and day of week. The smart phone can remotely create customized schedules and transmit them to the monitor.

10. 发明授权

US06894549B2 Ferroelectric non-volatile logic elements 有权
标题翻译：铁电非易失逻辑元件
公开(公告)号：US06894549B2
公开(公告)日：2005-05-17
申请号：US10613427
申请日：2003-07-03
申请人： Jarrod Eliason
发明人： Jarrod Eliason
IPC分类号： G11C11/22 , G11C19/00 , G11C19/28 , H01L21/8238 , H01L21/8246 , H01L27/092 , H01L27/105 , H03K3/356 , H03K3/45 , H03K19/185 , H03K3/037 , H03K3/12
CPC分类号： G11C11/22 , G11C19/005 , H03K3/356008 , H03K3/45
摘要： Various logic elements such as SR flip-flops, JK flip-flops, D-type flip-flops, master-slave flip-flops, parallel and serial shift registers, and the like are converted into non-volatile logic elements capable of retaining a current output logic state even though external power is removed or interrupted through the strategic addition of ferroelectric capacitors and supporting circuitry. In each case, the building blocks of a cross-coupled sense amplifier are identified within the logic element and the basic cell is modified and/or optimized for sensing performance.
摘要翻译：诸如SR触发器，JK触发器，D型触发器，主从触发器，并行和串行移位寄存器等各种逻辑元件被转换为能够保持即使通过铁电电容器和支持电路的战略添加来消除或中断外部电源，电流输出逻辑状态。在每种情况下，在逻辑元件内识别交叉耦合读出放大器的构建块，并且基本单元被修改和/或优化用于感测性能。

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