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1. 发明授权

US08559259B2 System and method for hidden refresh rate modification 有权
公开(公告)号：US08559259B2
公开(公告)日：2013-10-15
申请号：US13408566
申请日：2012-02-29
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

2. 发明申请

US20090225617A1 SYSTEM AND METHOD FOR HIDDEN-REFRESH RATE MODIFICATION 有权
标题翻译：系统和方法用于隐藏修正率修改
公开(公告)号：US20090225617A1
公开(公告)日：2009-09-10
申请号：US12464386
申请日：2009-05-12
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且当控制信号被断言时，刷新动态数据第一刷新率。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

3. 发明申请

US20060181936A1 Apparatus and methods for regulated voltage 有权
公开(公告)号：US20060181936A1
公开(公告)日：2006-08-17
申请号：US11059136
申请日：2005-02-15
申请人： John Schreck
发明人： John Schreck
IPC分类号： G11C7/00
CPC分类号： G11C5/147 , G05F1/46 , G05F1/618 , G11C11/4074
摘要： An electronic system according to various aspects of the present invention includes a memory and a supply regulation circuit having a regulated output to provide a selected voltage level. In one embodiment, the supply regulation circuit includes a reference voltage circuit connected to the supply and configured to receive a first voltage and a second voltage and provide a reference voltage and a control circuit connected to the reference voltage and configured to control the regulated voltage according to the reference voltage. The supply regulation circuit also includes an adjustment circuit controlled by the control circuit and configured to adjust the regulated voltage according to the reference voltage. The supply regulation circuit may also include a compensator circuit to provide additional adjustment to the regulated voltage.

4. 发明申请

US20050146962A1 Physically alternating sense amplifier activation 失效
公开(公告)号：US20050146962A1
公开(公告)日：2005-07-07
申请号：US11046895
申请日：2005-02-01
申请人： John Schreck
发明人： John Schreck
IPC分类号： G11C7/06 , G11C7/08 , G11C11/4091 , G11C7/02
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065
摘要： A memory device having banks of sense amplifiers comprising two types of sense amplifiers. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.

5. 发明授权

US06873562B2 Method and apparatus for standby power reduction in semiconductor devices 有权
标题翻译：用于半导体器件中待机功率降低的方法和装置
公开(公告)号：US06873562B2
公开(公告)日：2005-03-29
申请号：US10932542
申请日：2004-09-02
申请人： Jeff Koelling , John Schreck , Jon Morris , Rishad Omer
发明人： Jeff Koelling , John Schreck , Jon Morris , Rishad Omer
IPC分类号： G11C8/08 , G11C11/408 , G11C5/14
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/2227
摘要： A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off. When the decoupling transistor(s) is/are switched on prior to word line driving operation, the voltage on the local power supply node rises to the voltage of the global power supply node. Preferably, the control signal(s) controlling the decoupling transistor(s) are, or are derived from, control signals generated for purposes other than controlling the decoupling transistor.
摘要翻译：一种用于半导体存储器件的字线驱动电路。驱动电路中的一个或多个晶体管被制造成使得它们在某些条件下易受到栅极引起的二极管泄漏（GIDL）的影响。晶体管的一个端子耦合到本地电源节点，当在字线驱动器电路未驱动字线的待机状态下，该端子被保持在比全局电源节点的电压小的电压。在一个实施例中，本地电源节点通过至少一个解耦晶体管耦合到全局电源节点，所述去耦晶体管在其栅极处接收控制信号，并由vt连接的晶体管接收，使得本地电源节点当去耦晶体管断开时，其维持在不超过一个晶体管阈值电压的电平，小于全局电源节点电压。当在字线驱动操作之前，去耦晶体管被接通时，局部电源节点上的电压上升到全局电源节点的电压。优选地，控制去耦晶体管的控制信号或者是从除了控制去耦晶体管之外的目的产生的控制信号导出的。

6. 发明授权

US06819621B2 Method and apparatus for standby power reduction in semiconductor devices 有权
标题翻译：用于半导体器件中待机功率降低的方法和装置
公开(公告)号：US06819621B2
公开(公告)日：2004-11-16
申请号：US10334408
申请日：2002-12-31
申请人： Jeff Koelling , John Schreck , Jon Morris , Rishad Omer
发明人： Jeff Koelling , John Schreck , Jon Morris , Rishad Omer
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/2227
摘要： A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off. When the decoupling transistor(s) is/are switched on prior to word line driving operation, the voltage on the local power supply node rises to the voltage of the global power supply node. Preferably, the control signal(s) controlling the decoupling transistor(s) are, or are derived from, control signals generated for purposes other than controlling the decoupling transistor.
摘要翻译：一种用于半导体存储器件的字线驱动电路。驱动电路中的一个或多个晶体管被制造成使得它们在某些条件下易受到栅极引起的二极管泄漏（GIDL）的影响。晶体管的一个端子耦合到本地电源节点，当在字线驱动器电路未驱动字线的待机状态下，该端子被保持在比全局电源节点的电压小的电压。在一个实施例中，本地电源节点通过至少一个解耦晶体管耦合到全局电源节点，所述去耦晶体管在其栅极处接收控制信号，并由vt连接的晶体管接收，使得本地电源节点当去耦晶体管断开时，其维持在不超过一个晶体管阈值电压的电平，小于全局电源节点电压。当在字线驱动操作之前，去耦晶体管被接通时，局部电源节点上的电压上升到全局电源节点的电压。优选地，控制去耦晶体管的控制信号或者是从除了控制去耦晶体管之外的目的产生的控制信号导出的。

7. 发明授权

US06707729B2 Physically alternating sense amplifier activation 有权
标题翻译：物理交替感测放大器激活
公开(公告)号：US06707729B2
公开(公告)日：2004-03-16
申请号：US10075763
申请日：2002-02-15
申请人： John Schreck
发明人： John Schreck
IPC分类号： G11C706
CPC分类号： G11C11/4091 , G11C7/06 , G11C7/065
摘要： A memory device having banks of sense amplifiers with two different types of sense amplifiers is provided. A first driver used to activate the first type of sense amplifier is embedded into a first bank. A second driver used to activate a second type of sense amplifier is embedded into a second bank. This alternating physical placement of the first and second sense amplifier drivers within respective banks is repeated throughout the device. This alternating physical arrangement frees up the gaps and mini-gaps for other functions, reduces the buses used for sense amplifier activation signals and allows large drivers to be used, which improves the operation of the sense amplifiers and the device itself.
摘要翻译：提供了具有两个具有两种不同类型的读出放大器的读出放大器组的存储器件。用于激活第一类型的读出放大器的第一驱动器被嵌入到第一存储体中。用于激活第二类型的读出放大器的第二驱动器被嵌入到第二存储体中。在整个设备中重复在相应组内的第一和第二读出放大器驱动器的这种交替物理放置。这种交替的物理布置释放了其他功能的间隙和微型间隙，减少了用于读出放大器激活信号的总线，并允许使用大型驱动器，从而改善了读出放大器和器件本身的工作。

8. 发明授权

US06512705B1 Method and apparatus for standby power reduction in semiconductor devices 有权
标题翻译：用于半导体器件中待机功率降低的方法和装置
公开(公告)号：US06512705B1
公开(公告)日：2003-01-28
申请号：US09989964
申请日：2001-11-21
申请人： Jeff Koelling , John Schreck , Jon Morris , Rishad Omer
发明人： Jeff Koelling , John Schreck , Jon Morris , Rishad Omer
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C11/4085 , G11C2207/2227
摘要： A word line driver circuit for a semiconductor memory device. One or more transistors in the driver circuit are fabricated such that they are susceptible, under certain conditions, to gate-induced diode leakage (GIDL). One terminal of the transistors are coupled to a local supply node, which during standby conditions when the word line driver circuit is not driving a word line, is maintained at a voltage less than that of a global power supply node. In one embodiment, the local power supply node is coupled to the global power supply node by means of at least one decoupling transistor receiving a control signal at its gate and by a vt-connected transistor, such that the voltage on the local power supply node is maintained at a level not exceeding one transistor threshold voltage less than the global power supply node voltage when the decoupling transistor is off. When the decoupling transistor(s) is/are switched on prior to word line driving operation, the voltage on the local power supply node rises to the voltage of the global power supply node. Preferably, the control signal(s) controlling the decoupling transistor(s) are, or are derived from, control signals generated for purposes other than controlling the decoupling transistor.
摘要翻译：一种用于半导体存储器件的字线驱动电路。驱动电路中的一个或多个晶体管被制造成使得它们在某些条件下易受到栅极引起的二极管泄漏（GIDL）的影响。晶体管的一个端子耦合到本地电源节点，当在字线驱动器电路未驱动字线的待机状态下，该端子被保持在比全局电源节点的电压小的电压。在一个实施例中，本地电源节点通过至少一个解耦晶体管耦合到全局电源节点，该去耦晶体管在其栅极处接收控制信号，并由vt连接的晶体管接收，使得本地电源节点当去耦晶体管断开时，其维持在不超过一个晶体管阈值电压的电平，小于全局电源节点电压。当在字线驱动操作之前，去耦晶体管被接通时，局部电源节点上的电压上升到全局电源节点的电压。优选地，控制去耦晶体管的控制信号或者是从除了控制去耦晶体管之外的目的产生的控制信号导出的。

9. 发明授权

US08413007B2 Memory system and method using ECC with flag bit to identify modified data 有权
标题翻译：使用带有标志位的ECC的存储器系统和方法来识别修改的数据
公开(公告)号：US08413007B2
公开(公告)日：2013-04-02
申请号：US13026833
申请日：2011-02-14
申请人： J. Thomas Pawlowski , John Schreck
发明人： J. Thomas Pawlowski , John Schreck
IPC分类号： H03M13/00
CPC分类号： H03M13/151 , G06F11/10 , G06F11/1044 , G11C7/1006 , G11C11/406 , G11C29/44 , G11C29/52 , G11C2029/0411 , G11C2211/4062
摘要： A DRAM device includes an ECC generator/checker that generates ECC syndromes corresponding to items of data stored in the DRAM device. The DRAM device also includes an ECC controller that causes the ECC syndromes to be stored in the DRAM device. The ECC controller also causes a flag bit having a first value to be stored in the DRAM device when a corresponding ECC syndrome is stored. The ECC controller changes the flag bit to a second value whenever the corresponding data bits are modified, this indicating that the stored syndrome no longer corresponds to the stored data. In such case, the ECC controller causes a new ECC syndrome to be generated and stored, and the corresponding flag bit is reset to the first value. The flag bits may be checked in this manner during a reduced power refresh to ensure that the stored syndromes correspond to the stored data.
摘要翻译： DRAM装置包括ECC生成器/检查器，其生成与存储在DRAM装置中的数据对应的ECC校正子。 DRAM设备还包括ECC控制器，其使ECC校验子存储在DRAM设备中。当存储相应的ECC综合征时，ECC控制器还使得具有第一值的标志位被存储在DRAM设备中。每当相应的数据位被修改时，ECC控制器将标志位改变为第二值，这表示存储的校正符不再对应于存储的数据。在这种情况下，ECC控制器产生并存储新的ECC校验子，并且相应的标志位被复位到第一个值。可以在减少功率刷新期间以这种方式检查标志位，以确保所存储的校正子对应于所存储的数据。

10. 发明授权

US08130585B2 System and method for hidden-refresh rate modification 有权
标题翻译：隐藏刷新率修改的系统和方法
公开(公告)号：US08130585B2
公开(公告)日：2012-03-06
申请号：US12464386
申请日：2009-05-12
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

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