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1. 发明授权

US09679612B2 Techniques for providing a direct injection semiconductor memory device 有权
公开(公告)号：US09679612B2
公开(公告)日：2017-06-13
申请号：US14789453
申请日：2015-07-01
申请人： Micron Technology, Inc.
发明人： Eric Carman
IPC分类号： H01L27/102 , G11C5/02 , H01L27/108 , H01L29/73 , H01L29/78 , G11C11/402 , G11C16/26 , G11C5/06 , G11C7/00
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region coupled to a source line, a second region coupled to a bit line. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region coupled to a carrier injection line configured to inject charges into the body region through the second region.

2. 发明授权

US09530482B2 Methods of retaining and refreshing data in a thyristor random access memory 有权
标题翻译：在晶闸管随机存取存储器中保存和刷新数据的方法
公开(公告)号：US09530482B2
公开(公告)日：2016-12-27
申请号：US14841578
申请日：2015-08-31
申请人： Kilopass Technology, Inc.
发明人： Harry Luan , Bruce L. Bateman , Valery Axelrad , Charlie Cheng
IPC分类号： G11C11/34 , G11C11/39 , G11C11/402 , G11C11/401
CPC分类号： G11C11/39 , G11C11/401 , G11C11/402 , G11C11/406 , G11C11/4096 , H01L21/02532 , H01L21/26513 , H01L21/76224 , H01L27/1027 , H01L29/0649 , H01L29/66363 , H01L29/74
摘要： A volatile memory array using vertical thyristors is disclosed together with methods of operating the array to read, write, retain and refresh data stored therein.
摘要翻译：公开了使用垂直晶闸管的易失性存储器阵列以及操作阵列以读取，写入，保留和刷新存储在其中的数据的方法。

3. 发明授权

US09305631B1 Profiling method of address access count of semiconductor device and profiling circuit using the same 有权
标题翻译：半导体器件地址访问次数分析方法及其仿真电路
公开(公告)号：US09305631B1
公开(公告)日：2016-04-05
申请号：US14107669
申请日：2013-12-16
申请人： Samsung Electronics Co., Ltd.
发明人： Young Soo Sohn , Jong Pil Son , Jae Sung Kim , Chul Woo Park
IPC分类号： G06F12/10 , G11C11/406 , G11C11/402
CPC分类号： G11C11/40607 , G06F12/1018 , G11C7/00 , G11C11/402 , G11C11/406 , G11C11/40615 , G11C11/408
摘要： Provided is a profiling unit and method for profiling a number of times that an input/output address of a semiconductor device is accessed. The profiling unit includes a hash unit configured to produce at least one hash value by perform a hash operation on the input/output address, and a profiling circuit configured to profile the number of times that the input/output address is accessed by using the at least one hash value.
摘要翻译：提供了一种用于轮廓访问半导体器件的输入/输出地址的次数的分析单元和方法。简档单元包括散列单元，其被配置为通过对输入/输出地址执行散列操作来产生至少一个散列值;以及简档电路，其被配置为通过使用at来描述输入/输出地址被访问的次数最少一个哈希值。

4. 发明申请

US20160064400A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20160064400A1
公开(公告)日：2016-03-03
申请号：US14837261
申请日：2015-08-27
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Yoshiyuki KUROKAWA
IPC分类号： H01L27/115 , H01L23/528 , H01L29/786 , H01L27/06
CPC分类号： G11C11/402 , G11C11/34 , G11C11/565 , G11C2029/0403 , H01L21/8258 , H01L27/0688 , H01L27/1156 , H01L27/146 , H01L29/7869
摘要： To provide a memory cell for storing multilevel data that is less likely to be affected by variations in characteristics of transistors and that is capable of easily writing multilevel data in a short time and accurately reading it out. In writing, a current corresponding to multilevel data is supplied to the transistor in the memory cell and stored as the gate-drain voltage of the transistor in the memory cell. In reading, a current is supplied to the transistor in the transistor with the stored gate-drain voltage, and the multilevel data is obtained from the voltage supplied to generate a current that is equal to the current.
摘要翻译：提供用于存储不太可能受到晶体管特性变化影响的多电平数据的存储单元，并且能够在短时间内容易地编写多电平数据并准确地读出它。在写入时，对应于多电平数据的电流被提供给存储单元中的晶体管，并作为晶体管的栅极 - 漏极电压存储在存储单元中。在读取时，利用所存储的栅极 - 漏极电压向晶体管中的晶体管提供电流，并且从提供的电压获得多电平数据以产生等于电流的电流。

5. 发明授权

US09171605B1 Concentrated address detecting method of semiconductor device and concentrated address detecting circuit using the same 有权
标题翻译：半导体器件的集中地址检测方法及使用其的集中地址检测电路
公开(公告)号：US09171605B1
公开(公告)日：2015-10-27
申请号：US14103794
申请日：2013-12-11
申请人： Samsung Electronics Co., Ltd.
发明人： Young-Sik Kim , Won-Il Bae , Myeong-O Kim , Min-Soo Kim , Ho-Seok Seol , Min-Sang Park , Kyo-Min Sohn , Chi-Hwan Lee , Sang-Joon Hwang
IPC分类号： G11C11/408 , G11C11/406
CPC分类号： G11C11/40607 , G06F12/1018 , G11C7/00 , G11C11/402 , G11C11/406 , G11C11/40615 , G11C11/408
摘要： Provided is a method of detecting a concentrated address of a semiconductor device using an n-bit address. The method includes dividing the n-bit address into k groups, wherein each of n and k is an integer equal to or greater than 2, for each group of the k groups, detecting one or more concentrated sub addresses corresponding to the group, and generating at least one concentrated address by combining the one or more concentrated sub addresses for the k groups.
摘要翻译：提供了使用n位地址来检测半导体器件的集中地址的方法。该方法包括：对于k组中的每一组，将n位地址划分为k个组，其中n和k中的每一个是等于或大于2的整数，检测对应于该组的一个或多个集中子地址，以及通过组合用于k个组的一个或多个集中子地址来生成至少一个集中地址。

6. 发明授权

US09087554B1 Memory device, method for performing refresh operation of the memory device, and system including the same 有权
标题翻译：存储装置，用于执行存储装置的刷新操作的方法，以及包括该存储装置的系统
公开(公告)号：US09087554B1
公开(公告)日：2015-07-21
申请号：US14103402
申请日：2013-12-11
申请人： Samsung Electronics Co., Ltd.
发明人： Chul-Woo Park
IPC分类号： G11C7/00
CPC分类号： G11C11/40607 , G06F12/1018 , G11C7/00 , G11C11/402 , G11C11/406 , G11C11/40615 , G11C11/408
摘要： A method of performing a refresh operation of a memory device including a plurality of memory cells connected to a plurality of word lines. The method includes performing a table-based refresh operation on at least a first word line of the plurality of word lines in a first time period of a refresh cycle, and performing a detector-based refresh operation on at least a second word line of the plurality of word lines in a second time period of the refresh cycle. The first word line includes at least one memory cell predetermined to be a weak cell. The second word line includes at least one memory cell dynamically determined to be a weak cell.
摘要翻译：一种执行包括连接到多个字线的多个存储单元的存储器件的刷新操作的方法。所述方法包括在刷新周期的第一时间段内对所述多个字线的至少第一字线执行基于表的刷新操作，以及对所述多个字线的至少第二字线执行基于检测器的刷新操作，刷新周期的第二时间段中的多个字线。第一字线包括预定为弱电池的至少一个存储单元。第二字线包括动态地被确定为弱电池的至少一个存储器单元。

7. 发明申请

US20150187406A1 ACTIVE CONTROL DEVICE, SEMICONDUCTOR DEVICE AND SYSTEM INCLUDING THE SAME 有权
标题翻译：主动控制装置，半导体装置和包括其的系统
公开(公告)号：US20150187406A1
公开(公告)日：2015-07-02
申请号：US14231262
申请日：2014-03-31
申请人： SK hynix Inc.
发明人： Jin Ah KIM
IPC分类号： G11C11/4076 , G11C11/408 , G11C11/402
CPC分类号： G11C11/4076 , G11C8/12 , G11C11/402 , G11C11/40615 , G11C11/40618 , G11C11/4085
摘要： Disclosed herein are an active control device, a semiconductor device and system including the same. The active control device may include a refresh control unit configured for outputting a refresh signal by controlling a delay time for a refresh start time when a refresh operation is performed and a precharge signal generation unit configured for generating a bank precharge signal for precharging a bank in response to the refresh signal. The refresh control unit may include a refresh delay unit for delaying a bank-active signal for a specific time and outputting a delay signal, and the refresh delay unit may be operably coupled with a plurality of banks in common.
摘要翻译：这里公开了一种主动控制装置，半导体装置及包括该控制装置的系统。主动控制装置可以包括刷新控制单元，其被配置为通过控制执行刷新操作时的刷新开始时间的延迟时间来输出刷新信号;以及预充电信号生成单元，其被配置为产生用于对银行进行预充电的存储体预充电信号响应刷新信号。刷新控制单元可以包括刷新延迟单元，用于将特定时间的存储体活动信号延迟并输出延迟信号，并且刷新延迟单元可以与多个存储体共同操作地耦合。

8. 发明授权

US09036440B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09036440B2
公开(公告)日：2015-05-19
申请号：US13716418
申请日：2012-12-17
申请人： SK hynix Inc.
发明人： Choung-Ki Song
IPC分类号： G11C7/00 , G11C11/402 , G11C11/406
CPC分类号： G11C11/40607 , G11C11/402 , G11C11/40611 , G11C11/40615 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory device includes a memory cell array configured to include a plurality of word lines, a clock enable buffer configured to receive a clock enable signal, a plurality of command buffers configured to receive a plurality of commands, a refresh control unit configured to sequentially activate the plurality of word lines in a self-refresh mode, a command decoder configured to decode the clock enable signal and the plurality of commands, and to allow the refresh control unit to enter the self-refresh mode or exit from the self-refresh mode, and a buffer control unit configured to disable the plurality of command buffers when the clock enable signal is deactivated, and to enable the plurality of command buffers when the refresh control unit exits from the self-refresh mode.
摘要翻译：半导体存储器件包括配置为包括多个字线的存储单元阵列，被配置为接收时钟使能信号的时钟使能缓冲器，被配置为接收多个命令的多个命令缓冲器，配置为顺序地配置的刷新控制单元在自刷新模式下激活多个字线，命令解码器，被配置为对时钟使能信号和多个命令进行解码，并允许刷新控制单元进入自刷新模式或退出自刷新模式，以及缓冲器控制单元，被配置为当所述时钟使能信号被去激活时禁用所述多个命令缓冲器，并且当所述刷新控制单元退出所述自刷新模式时启用所述多个命令缓冲器。

9. 发明授权

US08964461B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08964461B2
公开(公告)日：2015-02-24
申请号：US14084386
申请日：2013-11-19
申请人： Micron Technology, Inc.
发明人： Yogesh Luthra
IPC分类号： G11C11/39 , G11C16/26 , H01L27/108 , H01L29/73 , H01L29/78 , G11C11/402 , H01L27/102
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one embodiment, the techniques may be realized as a method for biasing a direct injection semiconductor memory device including the steps of applying a first non-negative voltage potential to a first region via a bit line and applying a second non-negative voltage potential to a second region via a source line. The method may also include applying a third voltage potential to a word line, wherein the word line may be spaced apart from and capacitively to a body region that may be electrically floating and disposed between the first region and the second region. The method may further include applying a fourth positive voltage potential to a third region via a carrier injection line, wherein the third region may be disposed below at least one of the first region, the body region, and the second region.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个实施例中，技术可以被实现为用于偏置直接注入半导体存储器件的方法，包括以下步骤：通过位线将第一非负电压电位施加到第一区域，并将第二非负电压电位施加到经由源极线的第二区域。该方法还可以包括将第三电压电位施加到字线，其中字线可以与可以电浮动并且布置在第一区域和第二区域之间的体区间隔开并且电容化。该方法可以进一步包括经由载体注入管线将第四正电压电位施加到第三区域，其中第三区域可以设置在第一区域，体区域和第二区域中的至少一个之下。

10. 发明授权

US08861296B2 Memory refresh methods, memory section control circuits, and apparatuses 有权
标题翻译：存储器刷新方法，存储器部分控制电路和装置
公开(公告)号：US08861296B2
公开(公告)日：2014-10-14
申请号：US14084417
申请日：2013-11-19
申请人： Micron Technology, Inc.
发明人： John David Porter , Gi-Hong Kim
IPC分类号： G11C7/00 , G11C11/402 , G11C11/408 , G11C8/08 , G11C5/14 , G11C11/406 , G11C8/10
CPC分类号： G11C11/40615 , G11C5/147 , G11C8/08 , G11C8/10 , G11C11/402 , G11C11/406 , G11C11/4085 , G11C2211/4065 , G11C2211/4067
摘要： Apparatuses, memory section control circuits, and methods of refreshing memory are disclosed. An example apparatus includes a plurality of memory sections and a plurality of memory section control circuits. Each memory section control circuit is coupled to a respective one of the plurality of memory sections and includes a plurality of access line drivers, each of which includes a plurality of transistors having common coupled gates. During an operation of the apparatus a first voltage is provided to the commonly coupled gates of the transistors of at least some of the access line drivers of the memory section control circuit coupled to an active memory section and a second voltage is provided to the commonly coupled gates of the transistors of the access line drivers of the memory section control circuit coupled to an inactive memory section control circuit, wherein the first voltage is greater than the second voltage.
摘要翻译：公开了设备，存储器部分控制电路和刷新存储器的方法。示例性设备包括多个存储器部分和多个存储器部分控制电路。每个存储器部分控制电路耦合到多个存储器部分中的相应一个，并且包括多个存取线驱动器，每个存取线驱动器包括具有公共耦合栅极的多个晶体管。在装置的操作期间，将第一电压提供给耦合到有源存储器部分的存储器部分控制电路的至少一些存取线驱动器的晶体管的共同耦合的栅极，并且第二电压被提供给共同耦合的存储器部分控制电路的存取线驱动器的晶体管的栅极耦合到非活动存储器部分控制电路，其中第一电压大于第二电压。

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