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1. 发明申请

US20120155201A1 SYSTEM AND METHOD FOR HIDDEN REFRESH RATE MODIFICATION 有权
标题翻译：系统和方法用于隐藏修正率修改
公开(公告)号：US20120155201A1
公开(公告)日：2012-06-21
申请号：US13408566
申请日：2012-02-29
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C11/402 , G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

2. 发明授权

US07532532B2 System and method for hidden-refresh rate modification 有权
标题翻译：隐藏刷新率修改的系统和方法
公开(公告)号：US07532532B2
公开(公告)日：2009-05-12
申请号：US11140791
申请日：2005-05-31
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

3. 发明授权

US06721233B2 Circuit and method for reducing memory idle cycles 有权
标题翻译：减少内存空闲周期的电路和方法
公开(公告)号：US06721233B2
公开(公告)日：2004-04-13
申请号：US10365233
申请日：2003-02-11
申请人： John R. Wilford , Joseph T. Pawlowski
发明人： John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C11/419
摘要： An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.
摘要翻译：一个N位宽的同步突发定向静态随机存取存储器（SRAM）根据地址A0从其阵列同时读出全N位到N个锁存的读出放大器中，然后在X锁存的读出放大器中依次输出N / X位字突发周期。由于SRAM的阵列同时读出全部N位，阵列的地址总线被释放以锁存在下一个顺序地址A1中，所以与某些常规SRAM相比，数据输出不间断地继续。在将X个突发周期中的N / X位字逐步锁存到N个写入驱动器中之后，SRAM还将以全N位同时写入。这种同时写入释放阵列的地址总线以开始在下一个顺序地址A1中锁存，因此与某些常规SRAM相反，数据输入不间断地继续。

4. 发明授权

US6111812A Method and apparatus for adjusting control signal timing in a memory device 有权
标题翻译：用于调整存储器件中的控制信号定时的方法和装置
公开(公告)号：US6111812A
公开(公告)日：2000-08-29
申请号：US361025
申请日：1999-07-23
申请人： Dean Gans , John R. Wilford , Joseph T. Pawlowski
发明人： Dean Gans , John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C7/22 , G11C8/00
CPC分类号： G11C7/22
摘要： A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device includes clock sensing circuitry that receives the system clock signal and responsively produces a speed signal having a value corresponding to the frequency of the system clock signal. The clock sensing circuitry includes a plurality of series-connected time-delay circuits through which a signal derived from the system clock signal propagates. The clock sensing circuitry also includes a plurality of latch circuits, each coupled with a respective one of the time delay circuits and latching the value of the signal reaching the respective time delay circuit. The speed signal is then derived from these latched signal values, indicating through how many of the time-delay circuits the signal has propagated. The memory device also includes a control signal delay circuit that receives an internal memory control signal and the speed signal, and responsively produces a delayed control signal having a time delay corresponding to the speed signal value. The control signal delay circuit includes a plurality of series-connected time-delay circuits, with the memory control signal propagating through a selected number of these circuits. The control signal delay circuit also includes a selection circuit that receives the speed signal and correspondingly routes the memory control signal through the selected number of the time-delay circuits, with the selected number corresponding to the value of the speed signal.
摘要翻译：描述了一种用于根据外部应用的系统时钟速度来选择性地调整存储器件中的控制信号定时的方法和装置。存储器件包括时钟感测电路，其接收系统时钟信号并且响应地产生具有与系统时钟信号的频率对应的值的速度信号。时钟感测电路包括多个串联连接的时间延迟电路，通过该电路从系统时钟信号导出的信号传播。时钟感测电路还包括多个锁存电路，每个锁存电路与相应的一个时间延迟电路耦合，并锁存到达相应时间延迟电路的信号的值。然后从这些锁存的信号值导出速度信号，指示信号已经传播了多少个时间延迟电路。存储装置还包括控制信号延迟电路，其接收内部存储器控制信号和速度信号，并且响应地产生具有对应于速度信号值的时间延迟的延迟控制信号。控制信号延迟电路包括多个串联连接的时间延迟电路，存储器控制信号通过选定数量的这些电路传播。控制信号延迟电路还包括选择电路，其接收速度信号并相应地通过选定数量的时间延迟电路路由存储器控制信号，所选择的数字对应于速度信号的值。

5. 发明授权

US06570816B2 Circuit and method for reducing memory idle cycles 有权
公开(公告)号：US06570816B2
公开(公告)日：2003-05-27
申请号：US10274773
申请日：2002-10-21
申请人： John R. Wilford , Joseph T. Pawlowski
发明人： John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C11/419
摘要： An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

6. 发明授权

US06469954B1 Device and method for reducing idle cycles in a semiconductor memory device 有权
标题翻译：用于减少半导体存储器件中的空闲循环的装置和方法
公开(公告)号：US06469954B1
公开(公告)日：2002-10-22
申请号：US09642355
申请日：2000-08-21
申请人： John R. Wilford , Joseph T. Pawlowski
发明人： John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C11/419
摘要： An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.
摘要翻译：一个N位宽的同步突发定向静态随机存取存储器（SRAM）根据地址A0从其阵列同时读出全N位到N个锁存的读出放大器中，然后在X锁存的读出放大器中依次输出N / X位字突发周期。由于SRAM的阵列同时读出全部N位，阵列的地址总线被释放以锁存在下一个顺序地址A1中，所以与某些常规SRAM相比，数据输出不间断地继续。在将X个突发周期中的N / X位字逐步锁存到N个写入驱动器中之后，SRAM还将以全N位同时写入。这种同时写入释放阵列的地址总线以开始在下一个顺序地址A1中锁存，因此与某些常规SRAM相反，数据输入不间断地继续。

7. 发明授权

US06433403B1 Integrated circuit having temporary conductive path structure and method for forming the same 有权
标题翻译：具有临时导电路径结构的集成电路及其形成方法
公开(公告)号：US06433403B1
公开(公告)日：2002-08-13
申请号：US09295988
申请日：1999-04-21
申请人： John R. Wilford
发明人： John R. Wilford
IPC分类号： H01L2900
CPC分类号： H01L23/5258 , H01L21/28123 , H01L21/76892 , H01L21/823871 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.
摘要翻译：在集成电路中形成的牺牲导电路径，以将集成电路的半导体结构临时耦合在一起。牺牲导电路径包括牺牲区域，其在去除时能够切断电连续性。牺牲导电路径可用于在等离子体蚀刻步骤期间保护电容结构的栅极氧化物免受电荷相关损伤。牺牲结构将电容器结构的导电层临时耦合到衬底以释放任何电荷积累。牺牲区域在集成装置的操作之前将被去除以切断栅极和衬底之间的连接。牺牲导电路径可以由互连形成，并且通过等离子体蚀刻步骤去除牺牲区域。牺牲导电路径也可以由具有通过激光修整去除的牺牲区域的半导体熔丝形成。

8. 发明授权

US06317381B1 Method and system for adaptively adjusting control signal timing in a memory device 有权
标题翻译：用于自适应地调整存储器件中的控制信号定时的方法和系统
公开(公告)号：US06317381B1
公开(公告)日：2001-11-13
申请号：US09457429
申请日：1999-12-07
申请人： Dean Gans , John R. Wilford , John D. Porter
发明人： Dean Gans , John R. Wilford , John D. Porter
IPC分类号： G11C700
CPC分类号： G11C7/222 , G11C7/22 , G11C8/18
摘要： A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the frequency of an externally applied clock signal. The memory device includes clock sensing circuitry that receives the clock signal and responsively produces a plurality of speed signals that transition a plurality of times corresponding in number to the frequency of the clock signal. The memory device also includes a control signal delay circuit that receives a memory command signal and the speed signals, and responsively produces a delayed control signal having a time delay from the command signal corresponding to the number of transitions of the speed signal value. Significantly, the control signal is generated during a period of the clock signal that immediately follows a period of the clock signal when the delay of the control signal delay circuit is set.
摘要翻译：描述了用于根据外部施加的时钟信号的频率来选择性地调整存储器件中的控制信号定时的方法和装置。存储器件包括时钟感测电路，其接收时钟信号并且响应地产生多个速度信号，该速度信号在数量上对应于时钟信号的频率。存储装置还包括控制信号延迟电路，其接收存储器命令信号和速度信号，并响应于从与速度信号值的转换次数相对应的命令信号产生具有时间延迟的延迟控制信号。重要的是，当控制信号延迟电路的延迟被设置时，在紧接着时钟信号的周期的时钟信号的周期期间产生控制信号。

9. 发明授权

US06304511B1 Method and apparatus for adjusting control signal timing in a memory device 有权
标题翻译：用于调整存储器件中的控制信号定时的方法和装置
公开(公告)号：US06304511B1
公开(公告)日：2001-10-16
申请号：US09650475
申请日：2000-08-29
申请人： Dean Gans , John R. Wilford , Joseph T. Pawlowski
发明人： Dean Gans , John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C800
CPC分类号： G11C7/22
摘要： A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device includes clock sensing circuitry that receives the system clock signal and responsively produces a speed signal having a value corresponding to the frequency of the system clock signal. The clock sensing circuitry includes a plurality of series-connected time-delay circuits through which a signal derived from the system clock signal propagates. The clock sensing circuitry also includes a plurality of latch circuits, each coupled with a respective one of the time delay circuits and latching the value of the signal reaching the respective time delay circuit. The speed signal is then derived from these latched signal values, indicating through how many of the time-delay circuits the signal has propagated. The memory device also includes a control signal delay circuit that receives an internal memory control signal and the speed signal, and responsively produces a delayed control signal having a time delay corresponding to the speed signal value. The control signal delay circuit includes a plurality of series-connected time-delay circuits, with the memory control signal propagating through a selected number of these circuits. The control signal delay circuit also includes a selection circuit that receives the speed signal and correspondingly routes the memory control signal through the selected number of the time-delay circuits, with the selected number corresponding to the value of the speed signal.
摘要翻译：描述了一种用于根据外部应用的系统时钟速度来选择性地调整存储器件中的控制信号定时的方法和装置。存储器件包括时钟感测电路，其接收系统时钟信号并且响应地产生具有与系统时钟信号的频率对应的值的速度信号。时钟感测电路包括多个串联连接的时间延迟电路，通过该电路从系统时钟信号导出的信号传播。时钟感测电路还包括多个锁存电路，每个锁存电路与相应的一个时间延迟电路耦合，并锁存到达相应时间延迟电路的信号的值。然后从这些锁存的信号值导出速度信号，指示信号已经传播了多少个时间延迟电路。存储装置还包括控制信号延迟电路，其接收内部存储器控制信号和速度信号，并且响应地产生具有对应于速度信号值的时间延迟的延迟控制信号。控制信号延迟电路包括多个串联连接的时间延迟电路，存储器控制信号通过选定数量的这些电路传播。控制信号延迟电路还包括选择电路，其接收速度信号并相应地通过选定数量的时间延迟电路路由存储器控制信号，所选择的数字对应于速度信号的值。

10. 发明授权

US06272064B1 Memory with combined synchronous burst and bus efficient functionality 有权
标题翻译：具有组合同步突发和总线高效功能的内存
公开(公告)号：US06272064B1
公开(公告)日：2001-08-07
申请号：US09652775
申请日：2000-08-31
申请人： John R. Wilford , Dean Gans
发明人： John R. Wilford , Dean Gans
IPC分类号： G11C800
CPC分类号： G11C7/1072 , G11C7/1039 , G11C7/1045 , G11C7/1078 , G11C11/417
摘要： A memory device is described which is operable in both a synchronous mode and a bus efficient mode (BE). Address and data register circuitry provide multiple propagation paths which can be selected based upon the operating mode and function performed. These features allow one memory device to be manufactured for multiple commercial applications. The address and data register circuitry have first and second paths, wherein the second paths are longer than the first paths. Control circuitry is provided to select the desired paths. During a synchronous and BE read operations, the first path of both the address and data register circuitry is selected. During BE write operations, the second path of the address register circuitry is selected. If the BE is operating in non-pipelined mode, the second path of the data register circuitry is selected. Finally, if the BE is operating in pipelined mode, the first path of the data register circuitry is selected following a write operation, and the second path of the data register circuitry is selected following a read operation.
摘要翻译：描述了可在同步模式和总线高效模式（BE）中操作的存储器件。地址和数据寄存器电路提供可以基于所执行的操作模式和功能来选择的多个传播路径。这些功能允许为多个商业应用制造一个存储器件。地址和数据寄存器电路具有第一和第二路径，其中第二路径比第一路径长。提供控制电路以选择所需的路径。在同步和BE读操作期间，选择地址和数据寄存器电路的第一路径。在BE写操作期间，选择地址寄存器电路的第二路径。如果BE以非流水线模式运行，则选择数据寄存器电路的第二路径。最后，如果BE以流水线模式运行，则在写入操作之后选择数据寄存器电路的第一路径，并且在读取操作之后选择数据寄存器电路的第二路径。

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