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1. 发明授权

US08130585B2 System and method for hidden-refresh rate modification 有权
标题翻译：隐藏刷新率修改的系统和方法
公开(公告)号：US08130585B2
公开(公告)日：2012-03-06
申请号：US12464386
申请日：2009-05-12
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

2. 发明授权

US06621755B2 Testmode to increase acceleration in burn-in 有权
标题翻译：测试模式增加了老化的加速
公开(公告)号：US06621755B2
公开(公告)日：2003-09-16
申请号：US09943367
申请日：2001-08-30
申请人： Dean D. Gans , John R. Wilford
发明人： Dean D. Gans , John R. Wilford
IPC分类号： G11C700
CPC分类号： G11C29/26 , G11C11/41 , G11C2029/2602
摘要： A method and apparatus for simultaneously accessing multiple array blocks in a static random access memory (SRAM) device. During testing of the SRAM device, each memory cell in each memory array block is accessed to ensure proper functionality. By providing logic gates on each SRAM device, the testing can be accelerated by writing to multiple array blocks at the same time, rather than in series.
摘要翻译：一种用于同时访问静态随机存取存储器（SRAM）装置中的多个阵列块的方法和装置。在SRAM器件的测试期间，访问每个存储器阵列块中的每个存储器单元以确保正确的功能。通过在每个SRAM器件上提供逻辑门，可以通过同时写入多个阵列块而不是串联来加速测试。

3. 发明申请

US20120155201A1 SYSTEM AND METHOD FOR HIDDEN REFRESH RATE MODIFICATION 有权
标题翻译：系统和方法用于隐藏修正率修改
公开(公告)号：US20120155201A1
公开(公告)日：2012-06-21
申请号：US13408566
申请日：2012-02-29
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C11/402 , G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

4. 发明授权

US07532532B2 System and method for hidden-refresh rate modification 有权
标题翻译：隐藏刷新率修改的系统和方法
公开(公告)号：US07532532B2
公开(公告)日：2009-05-12
申请号：US11140791
申请日：2005-05-31
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且在控制信号被断言时以第一刷新率刷新动态数据。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

5. 发明授权

US06721233B2 Circuit and method for reducing memory idle cycles 有权
标题翻译：减少内存空闲周期的电路和方法
公开(公告)号：US06721233B2
公开(公告)日：2004-04-13
申请号：US10365233
申请日：2003-02-11
申请人： John R. Wilford , Joseph T. Pawlowski
发明人： John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C800
CPC分类号： G11C7/1018 , G11C11/419
摘要： An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.
摘要翻译：一个N位宽的同步突发定向静态随机存取存储器（SRAM）根据地址A0从其阵列同时读出全N位到N个锁存的读出放大器中，然后在X锁存的读出放大器中依次输出N / X位字突发周期。由于SRAM的阵列同时读出全部N位，阵列的地址总线被释放以锁存在下一个顺序地址A1中，所以与某些常规SRAM相比，数据输出不间断地继续。在将X个突发周期中的N / X位字逐步锁存到N个写入驱动器中之后，SRAM还将以全N位同时写入。这种同时写入释放阵列的地址总线以开始在下一个顺序地址A1中锁存，因此与某些常规SRAM相反，数据输入不间断地继续。

6. 发明授权

US6111812A Method and apparatus for adjusting control signal timing in a memory device 有权
标题翻译：用于调整存储器件中的控制信号定时的方法和装置
公开(公告)号：US6111812A
公开(公告)日：2000-08-29
申请号：US361025
申请日：1999-07-23
申请人： Dean Gans , John R. Wilford , Joseph T. Pawlowski
发明人： Dean Gans , John R. Wilford , Joseph T. Pawlowski
IPC分类号： G11C7/22 , G11C8/00
CPC分类号： G11C7/22
摘要： A method and apparatus is described for selectively adjusting control signal timing in a memory device as a function of the externally applied system clock speed. The memory device includes clock sensing circuitry that receives the system clock signal and responsively produces a speed signal having a value corresponding to the frequency of the system clock signal. The clock sensing circuitry includes a plurality of series-connected time-delay circuits through which a signal derived from the system clock signal propagates. The clock sensing circuitry also includes a plurality of latch circuits, each coupled with a respective one of the time delay circuits and latching the value of the signal reaching the respective time delay circuit. The speed signal is then derived from these latched signal values, indicating through how many of the time-delay circuits the signal has propagated. The memory device also includes a control signal delay circuit that receives an internal memory control signal and the speed signal, and responsively produces a delayed control signal having a time delay corresponding to the speed signal value. The control signal delay circuit includes a plurality of series-connected time-delay circuits, with the memory control signal propagating through a selected number of these circuits. The control signal delay circuit also includes a selection circuit that receives the speed signal and correspondingly routes the memory control signal through the selected number of the time-delay circuits, with the selected number corresponding to the value of the speed signal.
摘要翻译：描述了一种用于根据外部应用的系统时钟速度来选择性地调整存储器件中的控制信号定时的方法和装置。存储器件包括时钟感测电路，其接收系统时钟信号并且响应地产生具有与系统时钟信号的频率对应的值的速度信号。时钟感测电路包括多个串联连接的时间延迟电路，通过该电路从系统时钟信号导出的信号传播。时钟感测电路还包括多个锁存电路，每个锁存电路与相应的一个时间延迟电路耦合，并锁存到达相应时间延迟电路的信号的值。然后从这些锁存的信号值导出速度信号，指示信号已经传播了多少个时间延迟电路。存储装置还包括控制信号延迟电路，其接收内部存储器控制信号和速度信号，并且响应地产生具有对应于速度信号值的时间延迟的延迟控制信号。控制信号延迟电路包括多个串联连接的时间延迟电路，存储器控制信号通过选定数量的这些电路传播。控制信号延迟电路还包括选择电路，其接收速度信号并相应地通过选定数量的时间延迟电路路由存储器控制信号，所选择的数字对应于速度信号的值。

7. 发明授权

US08559259B2 System and method for hidden refresh rate modification 有权
公开(公告)号：US08559259B2
公开(公告)日：2013-10-15
申请号：US13408566
申请日：2012-02-29
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data at a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.

8. 发明申请

US20090225617A1 SYSTEM AND METHOD FOR HIDDEN-REFRESH RATE MODIFICATION 有权
标题翻译：系统和方法用于隐藏修正率修改
公开(公告)号：US20090225617A1
公开(公告)日：2009-09-10
申请号：US12464386
申请日：2009-05-12
申请人： John Schreck , John R. Wilford
发明人： John Schreck , John R. Wilford
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C11/402 , G11C11/406 , G11C11/40615 , G11C2211/4061
摘要： A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is refreshed at a second refresh rate when the control signal is deasserted for a predetermined duration. A hidden-refresh controller couples to an array of dynamic memory cells during a hidden-refresh of the array of dynamic memory cells. The hidden-refresh controller is further configured to monitor a control signal identifying a request from a processor at a memory device and refresh the dynamic data a first refresh rate when the control signal is asserted. The hidden-refresh controller is further configured to refresh the dynamic data at a second refresh rate when the control signal is deasserted for a predetermined duration.
摘要翻译：用于修改动态存储器单元的隐藏刷新率的系统和方法包括监视来自处理器的控制信号，并且当控制信号被断言时以第一刷新率执行动态数据的隐藏刷新。当控制信号被断言预定的持续时间时，动态数据以第二刷新率刷新。在动态存储器单元阵列的隐藏刷新期间，隐藏刷新控制器耦合到动态存储器单元阵列。隐藏刷新控制器还被配置为监视从存储器设备处的处理器识别请求的控制信号，并且当控制信号被断言时，刷新动态数据第一刷新率。所述隐藏刷新控制器还被配置为当所述控制信号被断言预定持续时间时，以第二刷新率刷新所述动态数据。

9. 发明授权

US06342723B1 Integrated circuit having temporary conductive path structure and method for forming the same 有权
公开(公告)号：US06342723B1
公开(公告)日：2002-01-29
申请号：US09295988
申请日：1999-04-21
申请人： John R. Wilford
发明人： John R. Wilford
IPC分类号： H01L2900
摘要： A sacrificial conductive path formed in an integrated circuit to temporarily couple together semiconductor structures of the integrated circuit. The sacrificial conductive path includes a sacrificial area that severs the electrical continuity when it is removed. The sacrificial conductive path may be used to protect the gate oxide of a capacitive structure from charge related damage during a plasma etch step. The sacrificial structure temporarily couples the conductive layer of the capacitor structure to the substrate to discharge any charge accumulation. The sacrificial area will be removed prior to operation of the integrated device to sever the connection between the gate and the substrate. The sacrificial conductive path may be formed by an interconnect, and the sacrificial area removed by a plasma etch step. The sacrificial conductive path may also be formed by a semiconductor fuse having a sacrificial area that is removed by laser trimming.

10. 发明授权

US6020762A Digital voltage translator and its method of operation 失效
标题翻译：数字电压转换器及其操作方法
公开(公告)号：US6020762A
公开(公告)日：2000-02-01
申请号：US105153
申请日：1998-06-26
申请人： John R. Wilford
发明人： John R. Wilford
IPC分类号： H03K19/00 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/0016
摘要： A signal translator circuit for particular use with low level logic signals is designed to accept a low level transitioning signal in a lower voltage range and output a signal transitioning within a higher voltage range. Circuitry is provided to ensure proper operation even at very low voltages. The circuitry which ensures proper operation at low voltages is selectively enabled when low input voltage input signals are used. In addition, the output signal is selectively disabled to allow downstream circuits to conserve energy during power up and power down cycles.
摘要翻译：用于特别用于低电平逻辑信号的信号转换器电路被设计为在较低电压范围内接受低电平转换信号，并输出在较高电压范围内的信号转换。提供电路以确保即使在非常低的电压下也能正常工作。当使用低输入电压输入信号时，选择性地使能确保低电压正常工作的电路。此外，输出信号被选择性禁止，以允许下游电路在上电和掉电周期期间节省能量。

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