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1. 发明授权

US08993434B2 Methods for forming layers on a substrate 有权
标题翻译：在基板上形成层的方法
公开(公告)号：US08993434B2
公开(公告)日：2015-03-31
申请号：US13226612
申请日：2011-09-07
申请人： Jick M. Yu , Rong Tao , Xinyu Fu
发明人： Jick M. Yu , Rong Tao , Xinyu Fu
IPC分类号： H01L21/4763 , H01L21/285 , H01L21/768
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76865 , H01L21/76868 , H01L21/76873 , H01L21/76879 , H01L2221/1089
摘要： Methods for forming layers on a substrate having one or more features formed therein are provided herein. In some embodiments, a method for forming layers on a substrate having one or more features formed therein may include depositing a seed layer within the one or more features; and etching the seed layer to remove at least a portion of the seed layer proximate an opening of the feature such that the seed layer comprises a first thickness disposed on a lower portion of a sidewall of the feature proximate a bottom of the feature and a second thickness disposed on an upper portion of the sidewall proximate the opening of the feature and wherein the first thickness is greater than the second thickness.
摘要翻译：本文提供了在其上形成有一个或多个特征的基底上形成层的方法。在一些实施例中，用于在其上形成有一个或多个特征的衬底上形成层的方法可包括在一个或多个特征内沉积晶种层; 并且蚀刻种子层以去除邻近特征的开口的种子层的至少一部分，使得种子层包括设置在靠近特征的底部的特征的侧壁的下部的第一厚度，以及第二厚度设置在靠近特征开口的侧壁的上部，并且其中第一厚度大于第二厚度。

2. 发明申请

US20130341794A1 ULTRA-THIN COPPER SEED LAYER FOR ELECTROPLATING INTO SMALL FEATURES 审中-公开
标题翻译：用于电镀到超小型特征的超薄铜层
公开(公告)号：US20130341794A1
公开(公告)日：2013-12-26
申请号：US13923979
申请日：2013-06-21
申请人： Jick M. YU , Rong TAO
发明人： Jick M. YU , Rong TAO
IPC分类号： C25D7/12 , H01L23/485
CPC分类号： C25D7/123 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L23/485 , H01L2221/1089 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and process are described that allow electroplating to fill sub-micron, high aspect ratio semiconductor substrate features using a non-copper/pre-electroplating layer on at least upper portions of side walls of the features, thereby providing reliable bottom up accumulation of the electroplating fill material in the feature. This apparatus and process eliminates feature filling material voids and enhances reliability of the electroplating in the diminishing size of features associated with future technology nodes of 22, 15, 11, and 8 nm. The presence of non-copper pre-electroplating material on the side walls allows the feature whose side walls, but not bottom surface, are lined with such pre-electroplating material (such as cobalt) to fill the feature using electroplated fill material accumulating from the bottom of the feature up to reliability and predictability and substantially void-free.
摘要翻译：描述了一种装置和方法，其允许电镀在特征的侧壁的至少上部上使用非铜/预电镀层填充亚微米，高纵横比的半导体衬底特征，由此提供可靠的自下而上的积累电镀填充材料的特点。该设备和工艺消除了特征填充材料的空隙，并增强了与22,15,11和8nm的未来技术节点相关联的特征尺寸减小的电镀的可靠性。在侧壁上存在非铜预电镀材料允许其侧壁但不是底表面衬有这种预电镀材料（例如钴）的特征，以使用从电镀填充材料积聚的电镀填充材料填充该特征功能的底部达到可靠性和可预测性，并且基本无效。

3. 发明授权

US08349724B2 Method for improving electromigration lifetime of copper interconnection by extended post anneal 失效
标题翻译：通过延伸后退火提高铜互连的电迁移寿命的方法
公开(公告)号：US08349724B2
公开(公告)日：2013-01-08
申请号：US12635528
申请日：2009-12-10
申请人： Xinyu Fu , Jick M. Yu
发明人： Xinyu Fu , Jick M. Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76838 , H01L21/76844 , H01L21/76855 , H01L21/76873 , H01L21/76877 , H01L21/76883
摘要： Methods for improving electromigration of copper interconnection structures are provided. In one embodiment, a method of annealing a microelectronic device including forming microelectronic features on a substrate, forming a contact structure over the microelectronic features, and forming a copper interconnection structure over the contact structure. A passivation layer is deposited over the copper interconnection structure and the substrate is subjected to a first anneal at a temperature of about 350° C. to 400° C. for a time duration between about 30 minutes to about 1 hour. The substrate is subjected to a second anneal at a temperature of about 150° C. to 300° C. for a time duration between about 24 to about 400 hours.
摘要翻译：提供了改善铜互连结构电迁移的方法。在一个实施例中，一种退火微电子器件的方法，包括在衬底上形成微电子特征，在微电子特征上形成接触结构，以及在接触结构上形成铜互连结构。在铜互连结构上沉积钝化层，并且将衬底在约350℃至400℃的温度下进行约30分钟至约1小时的持续时间的第一次退火。将衬底在约150℃至300℃的温度下进行约24至约400小时的持续时间的第二次退火。

4. 发明授权

US07737028B2 Selective ruthenium deposition on copper materials 有权
标题翻译：选择性钌沉积在铜材料上
公开(公告)号：US07737028B2
公开(公告)日：2010-06-15
申请号：US12240822
申请日：2008-09-29
申请人： Rongjun Wang , Hua Chung , Jick M. Yu , Praburam Gopalraja
发明人： Rongjun Wang , Hua Chung , Jick M. Yu , Praburam Gopalraja
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/28562 , C23C16/04 , C23C16/18 , H01L21/76846 , H01L21/76849 , H01L21/76868 , H01L21/76871 , H01L2221/1089
摘要： Embodiments of the invention provide processes for selectively forming a ruthenium-containing film on a copper surface over exposed dielectric surfaces. Thereafter, a copper bulk layer may be deposited on the ruthenium-containing film. In one embodiment, a method for forming layers on a substrate is provided which includes positioning a substrate within a processing chamber, wherein the substrate contains a copper-containing surface and a dielectric surface, exposing the substrate to a ruthenium precursor to selectively form a ruthenium-containing film over the copper-containing surface while leaving exposed the dielectric surface, and depositing a copper bulk layer over the ruthenium-containing film.
摘要翻译：本发明的实施方案提供了在暴露的电介质表面上在铜表面上选择性地形成含钌膜的方法。此后，可以将铜本体层沉积在含钌膜上。在一个实施例中，提供了一种用于在衬底上形成层的方法，其包括将衬底定位在处理室内，其中衬底包含含铜表面和电介质表面，将衬底暴露于钌前体以选择性地形成钌同时留下电介质表面，并在含钌膜上沉积铜体积层。

5. 发明授权

US07659204B2 Oxidized barrier layer 失效
标题翻译：氧化屏障层
公开(公告)号：US07659204B2
公开(公告)日：2010-02-09
申请号：US11691302
申请日：2007-03-26
申请人： Xianmin Tang , Hua Chung , Rongjun Wang , Praburam Gopalraja , Jick M. Yu , Jenn Yue Wang
发明人： Xianmin Tang , Hua Chung , Rongjun Wang , Praburam Gopalraja , Jick M. Yu , Jenn Yue Wang
IPC分类号： H01L21/44
CPC分类号： C23C14/046 , C23C14/0036 , C23C14/0641 , C23C14/083 , H01L21/2855 , H01L21/76844 , H01L21/76846 , H01L21/76856 , H01L21/76868 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method and resultant produce of forming barrier layer based on ruthenium tantalum in a via or other vertical interconnect structure through a dielectric layer in a multi-level metallization. The RuTa layer in a RuTa/RuTaN bilayer, which may form discontinuous islands, is actively oxidized, preferably in an oxygen plasma, to thereby bridge the gaps between the islands. Alternatively, ruthenium tantalum oxide is reactive sputtered onto the RuTaN or directly onto the underlying dielectric by plasma sputtering a RuTa target in the presence of oxygen.
摘要翻译：在多层金属化中通过介电层在通孔或其它垂直互连结构中形成基于钌钽的阻挡层的方法和所得产物。可能形成不连续岛的RuTa / RuTaN双层中的RuTa层优选在氧等离子体中被有效氧化，从而桥接岛之间的间隙。或者，通过在氧气存在下通过等离子体溅射RuTa靶，氧化钌钽氧化物反应性溅射到RuTaN上或直接沉积到下面的电介质上。

6. 发明申请

US20090215264A1 PROCESS FOR SELECTIVE GROWTH OF FILMS DURING ECP PLATING 失效
标题翻译： ECP镀层选择生长膜的工艺
公开(公告)号：US20090215264A1
公开(公告)日：2009-08-27
申请号：US12037578
申请日：2008-02-26
申请人： Jick M. Yu , Wei D. Wang , Rongjun Wang , Hua Chung
发明人： Jick M. Yu , Wei D. Wang , Rongjun Wang , Hua Chung
IPC分类号： H01L21/44
CPC分类号： H01L21/76879 , C25D5/02 , H01L21/76856 , H01L21/76859 , H01L21/76862 , H01L21/76873
摘要： Methods of controlling deposition of metal on field regions of a substrate in an electroplating process are provided. In one aspect, a dielectric layer is deposited under plasma on the field region of a patterned substrate, leaving a conductive surface exposed in the openings. Electroplating on the field region is reduced or eliminated, resulting in void-free features and minimal excess plating. In another aspect, a resistive layer, which may be a metal, is used in place of the dielectric. In a further aspect, the surface of the conductive field region is modified to change its chemical potential relative to the sidewalls and bottoms of the openings.
摘要翻译：提供了在电镀工艺中控制金属在基片的场区上沉积的方法。在一个方面，电介质层在等离子体上沉积在图案化衬底的场区上，留下在开口中暴露的导电表面。场区域上的电镀被减少或消除，导致无空隙特征和最小的多余电镀。在另一方面，可以使用可以是金属的电阻层来代替电介质。在另一方面，导电场区域的表面被修改以相对于开口的侧壁和底部改变其化学势。

7. 发明授权

US06884329B2 Diffusion enhanced ion plating for copper fill 失效
标题翻译：扩散增强离子电镀铜填充
公开(公告)号：US06884329B2
公开(公告)日：2005-04-26
申请号：US10340564
申请日：2003-01-10
申请人： Wei D. Wang , Anantha K. Subramani , Jianming Fu , Praburam Gopalraja , Jick M. Yu , Fusen Chen
发明人： Wei D. Wang , Anantha K. Subramani , Jianming Fu , Praburam Gopalraja , Jick M. Yu , Fusen Chen
IPC分类号： C23C14/04 , C23C14/34 , C23C14/54 , H01L21/285 , H01L21/768
CPC分类号： H01L21/76844 , C23C14/046 , C23C14/345 , C23C14/541 , H01L21/2855 , H01L21/76865 , H01L21/76877
摘要： A method of filling copper into a high-aspect ratio via by a plasma sputter process and allowing the elimination of electrochemical plating. In one aspect of the invention, the sputtering is divided into a first step performed at a low temperature of no more than 100° C. and with at least portions of high wafer bias, thereby filling a lower half of the hole, and a second step performed at a higher temperature, e.g., at least 200° C. and with at least portions of low wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma. In still another aspect, copper sputtering, even in the final fill phase, is performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter from the corners.
摘要翻译：一种通过等离子体溅射工艺将铜填充到高纵横比通孔并允许消除电化学电镀的方法。在本发明的一个方面，溅射被分为在不超过100℃的低温下进行的第一步骤和至少部分高晶片偏压，从而填充孔的下半部分，并且第二步骤步骤在较高的温度例如至少200℃进行，并且至少部分低晶片偏置以完成孔填充。在本发明的另一方面，将扩散促进气体如氢气加入到铜溅射等离子体中。在另一方面，即使在最终填充阶段，铜溅射也是通过多个低级和高级底座偏压循环进行的，以便在暴露的拐角上沉积铜并从拐角溅射。

8. 发明申请

US20100096273A1 CU SURFACE PLASMA TREATMENT TO IMPROVE GAPFILL WINDOW 失效
标题翻译： CU表面等离子体处理，以改善GAPFILL WINDOW
公开(公告)号：US20100096273A1
公开(公告)日：2010-04-22
申请号：US12256418
申请日：2008-10-22
申请人： Qian Luo , Arvind Sundarrajan , Hua Chung , Xianmin Tang , Jick M. Yu , Murali K. Narasimhan
发明人： Qian Luo , Arvind Sundarrajan , Hua Chung , Xianmin Tang , Jick M. Yu , Murali K. Narasimhan
IPC分类号： H01L21/288
CPC分类号： H01L21/76873 , C25D5/02 , C25D21/12 , H01L21/76843 , H01L21/76856 , H01L21/76862 , H01L21/76864 , H01L21/76877
摘要： A method and apparatus for selectively controlling deposition rate of conductive material during an electroplating process. Dopants are predominantly incorporated into a conductive seed layer on field regions of a substrate prior to filling openings in the field regions by electroplating. A substrate is positioned in one or more processing chambers, and barrier and conductive seed layers formed. A dopant precursor is provided to the chamber and ionized, with or without voltage bias. The dopant predominantly incorporates into the conductive seed layer on the field regions. Electrical conductivity of the conductive seed layer on the field regions is reduced relative to that of the conductive seed layer in the openings, resulting in low initial deposition rate of metal on the field regions during electroplating, and little or no void formation in the metal deposited in the openings.
摘要翻译：一种用于在电镀过程中选择性地控制导电材料的沉积速率的方法和装置。在通过电镀在场区域中填充开口之前，掺杂剂主要被结合到衬底的场区域上的导电种子层中。衬底被定位在一个或多个处理室中，形成阻挡层和导电种子层。在室内提供掺杂剂前体，并且在电压偏置或没有电压偏置的情况下电离。掺杂剂主要并入到场区域上的导电种子层中。导电种子层在场区域的电导率相对于开口中的导电种子层的导电率降低，导致电镀期间金属在场区域上的初始沉积速率较低，并且金属沉积中几乎没有或没有空隙形成在开口。

9. 发明授权

US07294574B2 Sputter deposition and etching of metallization seed layer for overhang and sidewall improvement 有权
标题翻译：金属化种子层的溅射沉积和蚀刻用于悬垂和侧壁改进
公开(公告)号：US07294574B2
公开(公告)日：2007-11-13
申请号：US10915139
申请日：2004-08-09
申请人： Peijun Ding , Fuhong Zhang , Hsien-Lung Yang , Michael A. Miller , Jianming Fu , Jick M. Yu , Zheng Xu , Fusen Chen
发明人： Peijun Ding , Fuhong Zhang , Hsien-Lung Yang , Michael A. Miller , Jianming Fu , Jick M. Yu , Zheng Xu , Fusen Chen
IPC分类号： H01L21/44
CPC分类号： H01L21/2855 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L2221/1089
摘要： An integrated sputtering method and reactor for copper or aluminum seed layers in which a plasma sputter reactor initially deposits a thin conformal layer onto a substrate including a high-aspect ratio hole subject to the formation of overhangs. After the seed deposition, the same sputter reactor is used to sputter etch the substrate with energetic light ions, especially helium, having an energy sufficiently low that it selectively etches the metallization to the heavier underlying barrier layer, for example, copper over tantalum or aluminum over titanium. An RF inductive coil generates the plasma during the sputtering etching while the target power is turned off. A final copper flash step deposits copper over the bare barrier field region before copper is electrochemically plated to fill the hole. The invention also includes a simultaneous sputter deposition and sputter etch, and an energetic ion processing of the copper seed sidewall.
摘要翻译：一种用于铜或铝种子层的集成溅射方法和反应器，其中等离子体溅射反应器最初将薄的共形层沉积到包括形成突出端的高纵横比孔的基板上。在种子沉积之后，使用相同的溅射反应器以能量足够低的能量的能量轻离子（特别是氦）溅射蚀刻衬底，以使其能够将金属化选择性地蚀刻到较重的下层阻挡层，例如钽或铝上的铜超过钛。 RF感应线圈在溅射蚀刻期间产生等离子体，同时关闭目标电源。在铜电化学镀以填充孔之前，最终的铜闪光步骤将铜沉积在裸露的屏障场区域上。本发明还包括同时溅射沉积和溅射蚀刻以及铜种子侧壁的能量离子处理。

10. 发明授权

US07265048B2 Reduction of copper dewetting by transition metal deposition 有权
标题翻译：通过过渡金属沉积减少铜的去湿
公开(公告)号：US07265048B2
公开(公告)日：2007-09-04
申请号：US11069514
申请日：2005-03-01
申请人： Hua Chung , Seshadri Ganguli , Christophe Marcadal , Jick M. Yu
发明人： Hua Chung , Seshadri Ganguli , Christophe Marcadal , Jick M. Yu
IPC分类号： H01L21/4763
CPC分类号： H01L21/76846 , H01L21/28556 , H01L21/76868 , H01L21/76873 , H01L2221/1089
摘要： A method and apparatus for forming layers on a substrate comprising depositing a metal seed layer on a substrate surface having apertures, depositing a transition metal layer over the copper seed layer, and depositing a bulk metal layer over the transition metal layer. Also a method and apparatus for forming a via through a dielectric to reveal metal at the base of the via, depositing a transition metal layer, and depositing a first metal layer on the transition metal layer. Additionally, a method and apparatus for depositing a transition metal layer on an exposed metal surface, and depositing a layer thereover selected from the group consisting of a capping layer and a low dielectric constant layer.
摘要翻译：一种用于在衬底上形成层的方法和装置，包括在具有孔的衬底表面上沉积金属籽晶层，在铜籽晶层上沉积过渡金属层，以及在过渡金属层上沉积体金属层。还有一种用于通过电介质形成通孔以在通孔底部露出金属的方法和装置，沉积过渡金属层，以及在过渡金属层上沉积第一金属层。另外，一种用于在暴露的金属表面上沉积过渡金属层并在其上沉积选自由封盖层和低介电常数层组成的层的方法和装置。

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