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1. 发明授权

US08224637B1 Method and apparatus for modeling transistors in an integrated circuit design 有权
标题翻译：用于在集成电路设计中建模晶体管的方法和装置
公开(公告)号：US08224637B1
公开(公告)日：2012-07-17
申请号：US11732194
申请日：2007-04-02
申请人： Jane W. Sowards , Shuxian Wu , Kaiman Chan
发明人： Jane W. Sowards , Shuxian Wu , Kaiman Chan
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An aspect of the invention relates to modeling a transistor in an integrated circuit design. Layout data for the integrated circuit design is obtained. A geometry relating the transistor to at least one well edge of at least one implant well is extracted from the layout data. An effective well proximity value for the transistor is calculated based on the at least one well edge using a complementary error function. The transistor is modeled using the effective well proximity value. In one embodiment, the effective well proximity value is added to a post-layout extracted netlist for the integrated circuit design. The integrated circuit design may be simulated using the post-layout extracted netlist. The effective well proximity value may be used to calculate a threshold voltage for the transistor during the step of simulating the integrated circuit.
摘要翻译：本发明的一个方面涉及对集成电路设计中的晶体管进行建模。获得集成电路设计的布局数据。从布局数据中提取将晶体管与至少一个注入井的至少一个阱边缘相关联的几何形状。基于使用互补误差函数的至少一个阱边缘来计算晶体管的有效阱接近值。晶体管使用有效的阱接近值进行建模。在一个实施例中，将有效阱接近值添加到用于集成电路设计的后布局提取的网表。可以使用后布局提取的网表来模拟集成电路设计。在模拟集成电路的步骤期间，可以使用有效阱接近度来计算晶体管的阈值电压。

2. 发明授权

US07932563B2 Techniques for improving transistor-to-transistor stress uniformity 有权
标题翻译：提高晶体管至晶体管应力均匀性的技术
公开(公告)号：US07932563B2
公开(公告)日：2011-04-26
申请号：US12363666
申请日：2009-01-30
申请人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
发明人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
IPC分类号： G06F17/50
CPC分类号： H01L21/823807 , H01L27/0207 , H01L27/11807 , H01L29/7843
摘要： An integrated circuit has a transistor with an active gate structure overlying an active diffusion area formed in a semiconductor substrate. A dummy gate structure is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer overlying the transistor array produces stress in a channel region of the transistor.
摘要翻译：集成电路具有覆盖在半导体衬底中形成的有源扩散区域的有源栅极结构的晶体管。在扩散区域上形成虚拟栅极结构，并与有源栅极结构分开一定距离（d2）。覆盖晶体管阵列的应力层在晶体管的沟道区域产生应力。

3. 发明申请

US20100193870A1 TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY 有权
标题翻译：改进晶体管到晶体管应力均匀性的技术
公开(公告)号：US20100193870A1
公开(公告)日：2010-08-05
申请号：US12363666
申请日：2009-01-30
申请人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
发明人： Jung-Ching J. Ho , Jane W. Sowards , Shuxian Wu
IPC分类号： H01L29/772 , G06F17/50 , H03K17/693
CPC分类号： H01L21/823807 , H01L27/0207 , H01L27/11807 , H01L29/7843
摘要： An integrated circuit (100) has a transistor with an active gate structure 108 overlying an active diffusion area 112 formed in a semiconductor substrate 126. A dummy gate structure 110 is formed over a diffusion area and separated from the active gate structure by a selected distance (d2). A stress layer (130) overlying the transistor array produces stress in a channel region (107) of the transistor.
摘要翻译：集成电路（100）具有晶体管，其具有覆盖形成在半导体衬底126中的有源扩散区域112的有源栅极结构108.伪栅极结构110形成在扩散区域上，并与有源栅极结构分开一定距离（d2）。覆盖晶体管阵列的应力层（130）在晶体管的沟道区（107）中产生应力。

4. 发明申请

US20090108337A1 Method of and circuit for protecting a transistor formed on a die 有权
标题翻译：用于保护形成在管芯上的晶体管的方法和电路
公开(公告)号：US20090108337A1
公开(公告)日：2009-04-30
申请号：US11977810
申请日：2007-10-26
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L27/0251
摘要： A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.
摘要翻译：公开了一种保护形成在集成电路的管芯上的晶体管的方法。该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

5. 发明授权

US08878337B1 Integrated circuit structure having a capacitor structured to reduce dishing of metal layers 有权
标题翻译：具有电容器的集成电路结构，其构造为减少金属层的凹陷
公开(公告)号：US08878337B1
公开(公告)日：2014-11-04
申请号：US13186279
申请日：2011-07-19
申请人： Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
发明人： Hong-Tsz Pan , Yun Wu , Shuxian Wu , Qi Lin , Bang-Thu Nguyen
IPC分类号： H01L21/02
CPC分类号： H01L29/94 , H01L21/3212 , H01L21/823842 , H01L27/0629 , H01L29/66181 , H01L29/66545 , H01L29/78
摘要： A method and integrated circuit structure for mitigating metal gate dishing resulting from chemical mechanical polishing. The integrated circuit structure comprises a first area comprising at least one first type device; a second area comprising at least one second type device; a third area comprising at least one capacitor having an uppermost layer of polysilicon, where the capacitor area is greater than a sum of the first and second areas. The method utilizes the polysilicon of the capacitor to mitigate metal gate dishing of a metal gate of at least one device.
摘要翻译：一种用于减轻由化学机械抛光引起的金属栅极凹陷的方法和集成电路结构。集成电路结构包括包括至少一个第一类型装置的第一区域; 第二区域，包括至少一个第二类型装置; 第三区域包括至少一个具有多晶硅最上层的电容器，其中电容器面积大于第一和第二区域的总和。该方法利用电容器的多晶硅来减轻至少一个器件的金属栅极的金属栅极凹陷。

6. 发明授权

US07772093B2 Method of and circuit for protecting a transistor formed on a die 有权
标题翻译：用于保护形成在管芯上的晶体管的方法和电路
公开(公告)号：US07772093B2
公开(公告)日：2010-08-10
申请号：US11977810
申请日：2007-10-26
申请人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
发明人： Yuhao Luo , Shuxian Wu , Xin X. Wu , Jae-Gyung Ahn , Deepak Kumar Nayak , Daniel Gitlin
IPC分类号： H01L21/326 , H01L21/479
CPC分类号： H01L27/0251
摘要： A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.
摘要翻译：公开了一种保护形成在集成电路的管芯上的晶体管的方法。该方法包括在晶片上形成晶体管的有源区; 在有源区上形成晶体管的栅极; 将初级接触耦合到晶体管的栅极; 在所述晶体管的栅极和保护元件之间耦合可编程元件; 以及通过可编程元件将保护元件与晶体管的栅极去耦合。还公开了用于保护形成在集成电路的管芯上的晶体管的电路。

7. 发明授权

US08427266B2 Integrated circuit inductor having a patterned ground shield 有权
标题翻译：具有图案化接地屏蔽的集成电路电感器
公开(公告)号：US08427266B2
公开(公告)日：2013-04-23
申请号：US13052310
申请日：2011-03-21
申请人： Zhaoyin D. Wu , Parag Upadhyahya , Xuewen Jiang , Jing Jing , Shuxian Wu
发明人： Zhaoyin D. Wu , Parag Upadhyahya , Xuewen Jiang , Jing Jing , Shuxian Wu
IPC分类号： H01F27/32
CPC分类号： H01F17/0006 , H01F2017/008 , H01L23/5225 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger.
摘要翻译：电感器结构可以在半导体集成电路（IC）内实现。电感器结构可以包括具有第一端子和第二端子的导电材料的线圈，每个端子均位于线圈的相对端。电感器结构可以包括图案化的接地屏蔽，其包括实现在位于导电材料的线圈和IC的衬底之间的IC处理层内的多个指状物。电感器结构还可以包括形成为包围线圈和图案化接地屏蔽的隔离壁。隔离壁可以联接到每个手指的一端。

8. 发明申请

US20120242446A1 INTEGRATED CIRCUIT INDUCTOR HAVING A PATTERNED GROUND SHIELD 有权
标题翻译：集成电路电感有一个图案地面
公开(公告)号：US20120242446A1
公开(公告)日：2012-09-27
申请号：US13052310
申请日：2011-03-21
申请人： Zhaoyin D. Wu , Parag Upadhyahya , Xuewen Jiang , Jing Jing , Shuxian Wu
发明人： Zhaoyin D. Wu , Parag Upadhyahya , Xuewen Jiang , Jing Jing , Shuxian Wu
IPC分类号： H01F27/29
CPC分类号： H01F17/0006 , H01F2017/008 , H01L23/5225 , H01L23/5227 , H01L28/10 , H01L2924/0002 , H01L2924/00
摘要： An inductor structure can be implemented within a semiconductor integrated circuit (IC). The inductor structure can include a coil of conductive material having a first terminal and a second terminal each located at an opposing end of the coil. The inductor structure can include a patterned ground shield including a plurality of fingers implemented within an IC process layer located between the coil of conductive material and a substrate of the IC. The inductor structure also can include an isolation wall formed to encompass the coil and the patterned ground shield. The isolation wall can be coupled to one end of each finger.
摘要翻译：电感器结构可以在半导体集成电路（IC）内实现。电感器结构可以包括具有第一端子和第二端子的导电材料的线圈，每个端子均位于线圈的相对端。电感器结构可以包括图案化的接地屏蔽，其包括实现在位于导电材料的线圈和IC的衬底之间的IC处理层内的多个指状物。电感器结构还可以包括形成为包围线圈和图案化接地屏蔽的隔离壁。隔离壁可以联接到每个手指的一端。

9. 发明授权

US08922309B1 Devices and methods for tuning an inductor 有权
标题翻译：用于调谐电感的装置和方法
公开(公告)号：US08922309B1
公开(公告)日：2014-12-30
申请号：US13274894
申请日：2011-10-17
申请人： Jing Jing , Shuxian Wu
发明人： Jing Jing , Shuxian Wu
IPC分类号： H01F30/14 , H01F21/08 , H01F21/02
CPC分类号： H01L23/5227 , H01F21/12 , H01F2021/125 , H01L23/5225 , H01L2924/0002 , H01L2924/00
摘要： An inductive device includes an inductor having an inductance associated therewith, and a tuning ring disposed around the inductor. The tuning ring has an inductance associated therewith, wherein the tuning ring is coupled to the inductor to establish a mutual inductance between the tuning ring and the inductor. The inductance of the inductor, the inductance of the tuning ring, and the mutual inductance between the tuning ring and the inductor contribute to a total inductance of the inductive device. The tuning ring is configurable, and is selectively configured to achieve a certain value for the mutual inductance, and a certain value for the inductance of the tuning ring, without changing a footprint of the tuning ring.
摘要翻译：感应装置包括具有与其相关的电感的电感器和设置在电感器周围的调谐环。调谐环具有与其相关联的电感，其中调谐环耦合到电感器以在调谐环和电感器之间建立互感。电感的电感，调谐环的电感以及调谐环和电感之间的互感有助于感应装置的总电感。调谐环是可配置的，并且被选择性地配置为实现互感的一定值，以及调谐环的电感的一定值，而不改变调谐环的占空比。

10. 发明授权

US08650020B1 Modeling second order effects for simulating transistor behavior 有权
标题翻译：建模模拟晶体管行为的二阶效应
公开(公告)号：US08650020B1
公开(公告)日：2014-02-11
申请号：US12363592
申请日：2009-01-30
申请人： Shuxian Wu , Tao Yu
发明人： Shuxian Wu , Tao Yu
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： Modeling and simulating behavior of a transistor are described. At least one sub-circuit model for modeling at least one second order effect associated with the transistor is obtained. At least one instance parameter for the at least one second order effect is obtained. Operation of a transistor behavior simulator is augmented with the at least one sub-circuit model populated with the at least one instance parameter such that the simulating of the behavior of the transistor produces data that takes into account the at least one second order effect. The at least one second order effect may be an LOD/eSiGe effect, a poly pitch effect, or a DSL boundary effect. Also described is a method for generation of a sub-circuit model.
摘要翻译：描述晶体管的建模和模拟行为。获得至少一个用于建模与晶体管相关联的至少一个二阶效应的子电路模型。获得至少一个二阶效应的至少一个实例参数。利用至少一个子电路模型来增加晶体管行为模拟器的操作，所述至少一个子电路模型填充有至少一个实例参数，使得模拟晶体管的行为产生考虑了至少一个二阶效应的数据。至少一个二阶效应可以是LOD / eSiGe效应，多音调效应或DSL边界效应。还描述了用于产生子电路模型的方法。

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