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1. 发明授权

US07719315B2 Programmable local clock buffer 失效
标题翻译：可编程本地时钟缓冲器
公开(公告)号：US07719315B2
公开(公告)日：2010-05-18
申请号：US11554666
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译：可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。扫描时钟前馈电路接收本地时钟并产生扫描时钟。数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

2. 发明申请

US20090199036A1 LSSD compatibility for GSD unified global clock buffers 有权
标题翻译： LSSD兼容GSD统一全局时钟缓冲区
公开(公告)号：US20090199036A1
公开(公告)日：2009-08-06
申请号：US12023337
申请日：2008-01-31
申请人： James D. Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
发明人： James D. Warnock , Wendel Dieter , David E. Lackey , William Vincent Huott , Leon Jacob Sigal , Louis Bernard Bushard , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G01R31/318594 , G01R31/318552
摘要： A method, system and program are provided for generating level sensitive scan design (LSSD) clock signals from a general scan design (GSD) clock buffer using an intermediate clock signal and one or more first mode control signals to generate a plurality of LSSD clock signals from an output section of the GSD clock buffer that receives the intermediate clock signal and the first mode control signal(s), where the GSD clock buffer is also configured to generate a plurality of GSD clock signals in response to receiving a GSD mode, generating an intermediate clock signal from the input section of the GSD clock buffer in response receiving a GSD mode signal.
摘要翻译：提供了一种方法，系统和程序，用于使用中间时钟信号和一个或多个第一模式控制信号从一般扫描设计（GSD）时钟缓冲器产生电平敏感扫描设计（LSSD）时钟信号，以产生多个LSSD时钟信号从GSD时钟缓冲器的输出部分接收中间时钟信号和第一模式控制信号，其中GSD时钟缓冲器还被配置为响应于接收GSD模式产生多个GSD时钟信号，产生来自GSD时钟缓冲器的输入部分的中间时钟信号响应于接收GSD模式信号。

3. 发明申请

US20090096486A1 Structure for Transmission Gate Multiplexer 审中-公开
标题翻译：传输门复用器的结构
公开(公告)号：US20090096486A1
公开(公告)日：2009-04-16
申请号：US12028940
申请日：2008-02-11
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005
摘要： A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术和设计结构包括从多个传输门组中选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

4. 发明授权

US07466165B1 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07466165B1
公开(公告)日：2008-12-16
申请号：US11854604
申请日：2007-09-13
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

5. 发明申请

US20080100360A1 PULSED LOCAL CLOCK BUFFER (LCB) CHARACTERIZATION RING OSCILLATOR 失效
标题翻译：脉冲本地时钟缓冲器（LCB）特征振荡器
公开(公告)号：US20080100360A1
公开(公告)日：2008-05-01
申请号：US11553014
申请日：2006-10-26
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G01R31/31727 , G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K5/156
摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.
摘要翻译：在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。输出驱动器输出脉宽调整信号。脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

6. 发明授权

US07225419B2 Methods for modeling latch transparency 有权
标题翻译：锁定透明度建模方法
公开(公告)号：US07225419B2
公开(公告)日：2007-05-29
申请号：US10962121
申请日：2004-10-08
申请人： Erwin Behnen , Jeffrey P. Soreff , James D. Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey P. Soreff , James D. Warnock , Dieter Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。提供了许多其他方面。

7. 发明授权

US07693701B2 Structure for a configurable low power high fan-in multiplexer 失效
标题翻译：可配置低功耗高风扇多路复用器的结构
公开(公告)号：US07693701B2
公开(公告)日：2010-04-06
申请号：US12132501
申请日：2008-06-03
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： G06F17/50 , H03K19/094
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

8. 发明授权

US07466164B1 Method and apparatus for a configurable low power high fan-in multiplexer 有权
标题翻译：用于可配置低功率高风扇多路复用器的方法和装置
公开(公告)号：US07466164B1
公开(公告)日：2008-12-16
申请号：US11759426
申请日：2007-06-07
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/94
CPC分类号： H03K19/0008 , H03K17/005
摘要： A configurable, low power high fan-in multiplexer (MUX) is disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高风扇多路复用器（MUX）。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

9. 发明申请

US20080303554A1 STRUCTURE FOR A CONFIGURABLE LOW POWER HIGH FAN-IN MULTIPLEXER 失效
标题翻译：可配置低功率高风扇多路复用器的结构
公开(公告)号：US20080303554A1
公开(公告)日：2008-12-11
申请号：US12132501
申请日：2008-06-03
申请人： Owen CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
发明人： Owen CHIANG , Christopher M. Durham , Peter J. Klim , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005 , H03K19/0008
摘要： A configurable, low power high fan-in multiplexer (MUX) and design structure thereof are disclosed. The MUX circuit includes multiple current control elements, which each include multiple inverters coupled to a transmission gate. Each current control element receives a data signal and a select signal that corresponds to the data signal. If a select signal exceeds a threshold value (e.g., a logical “1”), the select signal deactivates a pull-up transistor (e.g., a p-type field effect transistor), and the transmission gate enables the corresponding data signal to provide input to a logic gate (e.g., a NAND gate) coupled to the output of the MUX. If the select signal does not exceed the threshold value, the select signal activates the pull-up transistor, and the transmission gate prevents the corresponding data signal from providing input to the logic gate.
摘要翻译：公开了一种可配置的低功率高扇入多路复用器（MUX）及其设计结构。 MUX电路包括多个电流控制元件，每个电流控制元件包括耦合到传输门的多个反相器。每个电流控制元件接收对应于数据信号的数据信号和选择信号。如果选择信号超过阈值（例如，逻辑“1”），则选择信号去激活上拉晶体管（例如，p型场效应晶体管），并且传输门使相应的数据信号能够提供输入到与MUX的输出耦合的逻辑门（例如，NAND门）。如果选择信号不超过阈值，则选择信号激活上拉晶体管，并且传输门禁止相应的数据信号向逻辑门提供输入。

10. 发明授权

US07459950B2 Pulsed local clock buffer (LCB) characterization ring oscillator 失效
标题翻译：脉冲本地时钟缓冲器（LCB）表征环形振荡器
公开(公告)号：US07459950B2
公开(公告)日：2008-12-02
申请号：US11553014
申请日：2006-10-26
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G01R31/31727 , G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K5/156
摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.
摘要翻译：在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。输出驱动器输出脉宽调整信号。脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

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