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1. 发明授权

US08136061B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US08136061B2
公开(公告)日：2012-03-13
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

2. 发明授权

US07719315B2 Programmable local clock buffer 失效
标题翻译：可编程本地时钟缓冲器
公开(公告)号：US07719315B2
公开(公告)日：2010-05-18
申请号：US11554666
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译：可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。扫描时钟前馈电路接收本地时钟并产生扫描时钟。数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。

3. 发明申请

US20080100360A1 PULSED LOCAL CLOCK BUFFER (LCB) CHARACTERIZATION RING OSCILLATOR 失效
标题翻译：脉冲本地时钟缓冲器（LCB）特征振荡器
公开(公告)号：US20080100360A1
公开(公告)日：2008-05-01
申请号：US11553014
申请日：2006-10-26
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G01R31/31727 , G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K5/156
摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.
摘要翻译：在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。输出驱动器输出脉宽调整信号。脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

4. 发明授权

US07459950B2 Pulsed local clock buffer (LCB) characterization ring oscillator 失效
标题翻译：脉冲本地时钟缓冲器（LCB）表征环形振荡器
公开(公告)号：US07459950B2
公开(公告)日：2008-12-02
申请号：US11553014
申请日：2006-10-26
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K3/017
CPC分类号： H03K3/017 , G01R31/31727 , G06F1/10 , H03K3/0315 , H03K5/133 , H03K5/135 , H03K5/156
摘要： In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.
摘要翻译：在本发明的示例性实施例中，在半导体中制造的本地时钟缓冲器（LCB）接收全局时钟信号作为输入。 LCB实现了可操作地耦合到LCB的脉冲宽度控制器和形成环形振荡器的输出驱动器。输出驱动器输出脉宽调整信号。脉冲宽度调整信号的脉冲宽度可通过脉冲宽度控制器进行调节，并与频率相关于全局时钟信号。第二个环形振荡器（也称为nclk回路）也可以实现为服务器作为全局时钟信号。脉冲宽度控制器可用于精确调整脉宽调整信号的脉宽。可以实现脉冲宽度乘法器，以便直接观察和测量脉冲宽度调整信号的脉冲宽度。

5. 发明授权

US5896399A System and method for testing self-timed memory arrays 失效
标题翻译：用于测试自定时存储器阵列的系统和方法
公开(公告)号：US5896399A
公开(公告)日：1999-04-20
申请号：US763493
申请日：1996-12-11
申请人： George McNeil Lattimore , Michael Kevin Ciraula , Dieter F. Wendel , Manoj Kumar , Friedrich-Christian Wernicke
发明人： George McNeil Lattimore , Michael Kevin Ciraula , Dieter F. Wendel , Manoj Kumar , Friedrich-Christian Wernicke
IPC分类号： G11C29/14 , G11C29/00
CPC分类号： G11C29/14
摘要： The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.
摘要翻译：本发明以选择性方式将静态评估技术应用于存储器阵列，其允许阵列的某些部分使用该技术，并且仍保持阵列区域和定时不受正常操作的影响。本发明允许存储器阵列的解码功能在时钟周期的第一部分期间变为伪静态。此外，如果正在执行写入功能，则写入数据也保持为伪静态，并且在所有地址和数据均已稳定时，不会写入时钟周期的第二部分。即使存在非功能性赛跑路径，本发明也可用于系统调试，产品开机或老化。在自定时存储器阵列中测试和刻录的系统和方法包括应用于解码功能的静态评估电路和阵列的写入功能，用于保持地址或写入对于循环的第一部分无效的数据的电路，用于激活用于周期的第二部分的地址或写入数据的电路，以及用于确保阵列正确复位的电路。

6. 发明授权

US06502224B2 Method and apparatus for synthesizing levelized logic 失效
标题翻译：用于合成等级化逻辑的方法和装置
公开(公告)号：US06502224B2
公开(公告)日：2002-12-31
申请号：US09833413
申请日：2001-04-12
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F1750
CPC分类号： G06F17/505 , G06F17/5054 , Y02T10/82
摘要： A method and apparatus for synthesizing logic circuits with synchronized outputs is disclosed. A logic designer selects a fixed number of levels in which to synthesize the circuit, each level implementing a plurality of different logic function all having the same propagation delay. Circuit outputs are synchronized by ensuring that each logic function is synthesized by connecting logic functions from level to level such that each signal path passes through each level once and only once.
摘要翻译：公开了一种用于合成具有同步输出的逻辑电路的方法和装置。逻辑设计者选择固定数量的电平来合成电路，每个级别实现多个具有相同传播延迟的不同逻辑功能。通过确保每个逻辑功能通过将逻辑功能从电平连接到电平来合成，使得每个信号路径通过每个级别一次且仅一次，从而同步电路输出。

7. 发明申请

US20080189670A1 METHOD OF LOGIC CIRCUIT SYNTHESIS AND DESIGN USING A DYNAMIC CIRCUIT LIBRARY 有权
标题翻译：使用动态电路图的逻辑电路合成和设计方法
公开(公告)号：US20080189670A1
公开(公告)日：2008-08-07
申请号：US12060768
申请日：2008-04-01
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block and then performing logic synthesis for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit is produced, the circuit design method includes eliminating unnecessary devices from the intermediate circuit to produce a final logic circuit, and then sizing the devices in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块，然后执行用于要实现的预定逻辑运算的逻辑合成。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计，其必然包括一系列动态电路块，每个动态电路块与单个复位信号相关联。一旦生成了中间电路，电路设计方法包括从中间电路中消除不必要的设备，产生最终的逻辑电路，然后对最终电路中的器件进行尺寸调整以完成设计。

8. 发明授权

US07372305B1 Scannable dynamic logic latch circuit 失效
标题翻译：可扫描动态逻辑锁存电路
公开(公告)号：US07372305B1
公开(公告)日：2008-05-13
申请号：US11554685
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/096
CPC分类号： H03K19/096 , G01R31/318541
摘要： A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.
摘要翻译：可扫描的锁存器包含具有至少一个具有执行正常布尔逻辑运算的逻辑树的动态逻辑门的逻辑前端。动态逻辑门被组合成扫描下拉逻辑树，其被耦合到扫描保持锁存器输出和动态逻辑门的动态节点。扫描时钟和正常时钟确定逻辑电路是处于正常逻辑模式还是处于扫描测试模式。静态输出锁存器具有至少一个作为动态节点的响应逻辑状态的输入。响应于扫描时钟或正常时钟的逻辑状态，动态节点的评估状态由动态逻辑门的逻辑树或扫描电路的扫描下拉逻辑树来设置。

9. 发明申请

US20080100344A1 SCANNABLE DYNAMIC LOGIC LATCH CIRCUIT 失效
标题翻译： SCANNABLE动态逻辑锁存电路
公开(公告)号：US20080100344A1
公开(公告)日：2008-05-01
申请号：US11554685
申请日：2006-10-31
申请人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
发明人： Hung C. Ngo , Jente B. Kuang , James D. Warnock , Dieter F. Wendel
IPC分类号： H03K19/096
CPC分类号： H03K19/096 , G01R31/318541
摘要： A scannable latch incorporates a logic front end that has at least one dynamic logic gate that has a logic tree that perform the normal Boolean logic operation. The dynamic logic gate is combined a scan pull-down logic tree that is coupled to a scan hold latch output and to the dynamic node of the dynamic logic gate. A scan clock and a normal clock determine whether the logic circuitry is in the normal logic mode or in the scan test mode. A static output latch has at least one input that is responsive logic state of a dynamic node. The evaluated state of the dynamic node is set by either the logic tree of the dynamic logic gate or the scan pull-down logic tree of the scan circuitry in response to the logic state of the scan clock or the normal clock.
摘要翻译：可扫描的锁存器包含具有至少一个具有执行正常布尔逻辑运算的逻辑树的动态逻辑门的逻辑前端。动态逻辑门被组合成扫描下拉逻辑树，其被耦合到扫描保持锁存器输出和动态逻辑门的动态节点。扫描时钟和正常时钟确定逻辑电路是处于正常逻辑模式还是处于扫描测试模式。静态输出锁存器具有至少一个作为动态节点的响应逻辑状态的输入。响应于扫描时钟或正常时钟的逻辑状态，动态节点的评估状态由动态逻辑门的逻辑树或扫描电路的扫描下拉逻辑树来设置。

10. 发明授权

US07363609B2 Method of logic circuit synthesis and design using a dynamic circuit library 有权
标题翻译：使用动态电路库的逻辑电路合成与设计方法
公开(公告)号：US07363609B2
公开(公告)日：2008-04-22
申请号：US09915437
申请日：2001-07-26
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Stephen Douglas Posluszny , Joel Abraham Silberman , Osamu Takahashi , Dieter F. Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The circuit library available for logic synthesis is limited to a single dynamic circuit block or logic synthesis block. The circuit design method includes first defining the logic synthesis block (16) and then performing logic synthesis (17) for a predetermined logical operation to be implemented. The logic synthesis step constrained to the single logic synthesis block produces an intermediate circuit design (29) which necessarily comprises a series of dynamic circuit blocks, each associated with a single reset signal. Once the intermediate circuit (29) is produced, the circuit design method includes eliminating unnecessary devices (46) from the intermediate circuit (29) to produce a final logic circuit, and then sizing the devices (48) in the final circuit to complete the design.
摘要翻译：可用于逻辑合成的电路库限于单个动态电路块或逻辑合成块。电路设计方法包括首先定义逻辑合成块（16），然后执行用于要实现的预定逻辑运算的逻辑合成（17）。限制到单个逻辑合成块的逻辑合成步骤产生中间电路设计（29），其必须包括一系列与单个复位信号相关联的动态电路块。一旦产生中间电路（29），电路设计方法包括从中间电路（29）消除不必要的装置（46）以产生最终的逻辑电路，然后对最终电路中的装置（48）进行尺寸调整以完成设计。

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