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1. 发明授权

US07225419B2 Methods for modeling latch transparency 有权
标题翻译：锁定透明度建模方法
公开(公告)号：US07225419B2
公开(公告)日：2007-05-29
申请号：US10962121
申请日：2004-10-08
申请人： Erwin Behnen , Jeffrey P. Soreff , James D. Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey P. Soreff , James D. Warnock , Dieter Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。提供了许多其他方面。

2. 发明授权

US07080335B2 Methods for modeling latch transparency 失效
标题翻译：锁定透明度建模方法
公开(公告)号：US07080335B2
公开(公告)日：2006-07-18
申请号：US10672500
申请日：2003-09-26
申请人： Erwin Behnen , Jeffrey P. Soreff , James D. Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey P. Soreff , James D. Warnock , Dieter Wendel
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。提供了许多其他方面。

3. 发明申请

US20080077889A1 PARAMETERIZED SEMICONDUCTOR CHIP CELLS AND OPTIMIZATION OF THE SAME 审中-公开
标题翻译：参数化半导体芯片细胞及其优化
公开(公告)号：US20080077889A1
公开(公告)日：2008-03-27
申请号：US11533814
申请日：2006-09-21
申请人： Erwin Behnen , Gregory A. Northrop , James D. Warnock , Dieter Wendel , Pieter Joseph Woeltgens
发明人： Erwin Behnen , Gregory A. Northrop , James D. Warnock , Dieter Wendel , Pieter Joseph Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method is provided for designing an integrated circuit utilizing an arrangement of at least one library cell having a plurality of parameterized input connection points disposed along a rod, a plurality of parameterized output connection points disposed along a wire and a cell structure to which the rod and wire are electrically connected; routing and making input and output connections to the library cells at the parameterized input connection points and the parameterized output connection points to satisfy design specifications of the integrated circuit. After determining which parameterized input connection points and parameterized output connection points are unused, the unused parameterized input connection points and parameterized output connection points are removed from each library cell of the integrated circuit design.
摘要翻译：提供了一种利用至少一个库单元的布置来设计集成电路的方法，所述库单元具有沿着杆布置的多个参数化的输入连接点，沿着导线设置的多个参数化的输出连接点以及单元结构，所述杆电线电连接; 在参数化的输入连接点和参数化的输出连接点上路由并输入到库单元的输入和输出连接，以满足集成电路的设计规范。在确定哪些参数化输入连接点和参数化输出连接点未使用之后，将从集成电路设计的每个库单元中删除未使用的参数化输入连接点和参数化输出连接点。

4. 发明申请

US20050071794A1 Methods for modeling latch transparency 有权
标题翻译：锁定透明度建模方法
公开(公告)号：US20050071794A1
公开(公告)日：2005-03-31
申请号：US10962121
申请日：2004-10-08
申请人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.
摘要翻译：在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。提供了许多其他方面。

5. 发明申请

US20050071790A1 Methods for modeling latch transparency 失效
公开(公告)号：US20050071790A1
公开(公告)日：2005-03-31
申请号：US10672500
申请日：2003-09-26
申请人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
发明人： Erwin Behnen , Jeffrey Soreff , James Warnock , Dieter Wendel
IPC分类号： G06F9/45 , G06F17/50
CPC分类号： G06F17/5022
摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

6. 发明授权

US08354858B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US08354858B2
公开(公告)日：2013-01-15
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

7. 发明授权

US07888959B2 Apparatus and method for hardening latches in SOI CMOS devices 有权
标题翻译：用于硬化SOI CMOS器件中的锁存器的装置和方法
公开(公告)号：US07888959B2
公开(公告)日：2011-02-15
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： G01R31/26
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

8. 发明申请

US20110102042A1 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES 有权
标题翻译：用于在SOI CMOS器件中硬化栅极的装置和方法
公开(公告)号：US20110102042A1
公开(公告)日：2011-05-05
申请号：US12987106
申请日：2011-01-08
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： H03K3/00
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

9. 发明申请

US20090134925A1 APPARATUS AND METHOD FOR HARDENING LATCHES IN SOI CMOS DEVICES 有权
标题翻译：用于在SOI CMOS器件中硬化栅极的装置和方法
公开(公告)号：US20090134925A1
公开(公告)日：2009-05-28
申请号：US11857596
申请日：2007-09-19
申请人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
发明人： Ethan H. Cannon , AJ KleinOsowski , K. Paul Muller , Tak H. Ning , Philip J. Oldiges , Leon J. Sigal , James D. Warnock , Dieter Wendel
IPC分类号： H03K3/356 , H03K3/00
CPC分类号： H03K3/356156 , H03K3/0375
摘要： A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.
摘要翻译：确定特定电路内分别被硬化晶体管替代的一个或多个晶体管的方法包括：鉴定为不需要硬化一个或多个晶体管; 识别作为硬化的候选者，电路中的每个晶体管先前未被识别为不需要硬化; 并且使用硬化晶体管代替被鉴定为硬化候选的晶体管。该电路是锁存器，晶体管是SOI CMOS FET。晶体管也是SOI晶体管。串联晶体管包括具有共享源极/漏极区域的第一和第二串联连接的晶体管，由此第一串联晶体管的漏极与第二串联晶体管的源极合并。

10. 发明授权

US06822500B1 Methods and apparatus for operating master-slave latches 有权
标题翻译：操作主从锁存器的方法和装置
公开(公告)号：US06822500B1
公开(公告)日：2004-11-23
申请号：US10651176
申请日：2003-08-28
申请人： James D. Warnock , Dieter Wendel
发明人： James D. Warnock , Dieter Wendel
IPC分类号： G06F104
CPC分类号： G06F1/06 , H03K3/0372
摘要： A method for operating a master latch and a slave latch coupled to the master latch includes the steps of attempting to operate the master latch and the slave latch in a first mode in which (1) the master latch is held in an open condition; and (2) the slave latch is pulsed so as to latch data passed through the open master latch. If the master latch and the slave latch do not operate in the first mode, the master latch and the slave latch are operated in a second mode in which (1) a first clock signal is employed to latch data with the master latch; and (2) a second clock signal is employed to latch data latched by the master latch with the slave latch.
摘要翻译：用于操作耦合到主锁存器的主锁存器和从锁存器的方法包括以第一模式操作主锁存器和从锁存器的步骤，其中（1）主锁存器保持在打开状态; 和（2）从锁存器被脉冲以便锁存通过打开的主锁存器的数据。如果主锁存器和从锁存器不在第一模式下操作，则主锁存器和从锁存器在第二模式下操作，其中（1）使用第一时钟信号来与主锁存器锁存数据; 和（2）第二时钟信号用于锁存由主锁存器锁存的数据与从锁存器。

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