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1. 发明授权

US07224594B2 Glitch protect valid cell and method for maintaining a desired state value 有权
标题翻译：毛刺保护有效的单元格和方法以保持所需的状态值
公开(公告)号：US07224594B2
公开(公告)日：2007-05-29
申请号：US11184346
申请日：2005-07-19
申请人： Derick G. Behrends , Chad A. Adams , Ryan C. Kivimagi , Anthony G. Aipperspach , Robert N. Krentler
发明人： Derick G. Behrends , Chad A. Adams , Ryan C. Kivimagi , Anthony G. Aipperspach , Robert N. Krentler
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C7/24
摘要： A glitch protect valid cell and method for maintaining a desired logic state value. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit. The glitch protect circuit includes a propagation delay assembly coupled to a restore assembly. The propagation delay assembly includes a first pull down network coupled to a NOR gate. The restore assembly includes a second pull down network coupled to the propagation delay assembly. Responsive to a glitch signal and timing signal, the first pull down network resets the initial state value of a true valid bit to ultimately enable a pull up network in the NOR gate. Responsive to enablement of the NOR gate pull up network, the second pull down network resets the complement valid bit in the memory element to consequently restore the initial state of the true valid bit.
摘要翻译：毛刺保护有效的单元格和方法，用于维护所需的逻辑状态值。毛刺保护有效单元包括存储元件，状态机和毛刺保护电路。毛刺保护电路包括耦合到恢复组件的传播延迟组件。传播延迟组件包括耦合到或非门的第一下拉网络。恢复组件包括耦合到传播延迟组件的第二下拉网络。响应于毛刺信号和定时信号，第一个下拉网络复位真正有效位的初始状态值，以最终实现NOR门中的上拉网络。响应于启动NOR门上拉网络，第二个下拉网络复位存储器元件中的补码有效位，从而恢复真有效位的初始状态。

2. 发明申请

US20090072863A1 Transmission Gate Multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US20090072863A1
公开(公告)日：2009-03-19
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20 , G06F9/305
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

3. 发明申请

US20080215941A1 Double-edge triggered scannable pulsed flip-flop for high frequency and/or low power applications 审中-公开
标题翻译：用于高频和/或低功率应用的双边沿触发可扫描脉冲触发器
公开(公告)号：US20080215941A1
公开(公告)日：2008-09-04
申请号：US12123107
申请日：2008-05-19
申请人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
发明人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/318502 , G01R31/318575 , G01R31/318591
摘要： A design structure embodied in a machine readable medium used in a design process, includes a circuit for data storage. The circuit includes a double edge clock generation circuit for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock; a scan clock generation circuit for generating first and second scan clock signals; a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, the scannable pulse flip-flop circuit including a scan input and a scan output connected with the internal storage node, and receptive to the pulse clock signal and the scan clock signals. The scannable pulse flip-flop circuit is configured to be operable in a function mode of operation and a scan mode of operation.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括用于数据存储的电路。该电路包括一个双边沿时钟产生电路，用于产生具有用于系统时钟的每个时钟周期的第一和第二时钟脉冲的脉冲时钟信号; 扫描时钟产生电路，用于产生第一和第二扫描时钟信号; 具有与内部存储节点连接的数据输入和数据输出的可扫描脉冲触发器电路，所述可扫描脉冲触发器电路包括与内部存储节点连接的扫描输入和扫描输出，并且可接受脉冲时钟信号和扫描时钟信号。可扫描脉冲触发器电路被配置为在操作的功能模式和扫描操作模式下可操作。

4. 发明授权

US07633316B2 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07633316B2
公开(公告)日：2009-12-15
申请号：US12256582
申请日：2008-10-23
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

5. 发明申请

US20090096486A1 Structure for Transmission Gate Multiplexer 审中-公开
标题翻译：传输门复用器的结构
公开(公告)号：US20090096486A1
公开(公告)日：2009-04-16
申请号：US12028940
申请日：2008-02-11
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/005
摘要： A technique and design structure for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术和设计结构包括从多个传输门组中选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

6. 发明授权

US07466165B1 Transmission gate multiplexer 失效
标题翻译：传输门复用器
公开(公告)号：US07466165B1
公开(公告)日：2008-12-16
申请号：US11854604
申请日：2007-09-13
申请人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
发明人： Owen Chiang , Christopher M. Durham , Peter J. Klim , Robert N. Krentler , James D. Warnock
IPC分类号： H03K19/20
CPC分类号： H03K17/002
摘要： A technique for operating a multiplexer includes selecting, from multiple transmission gate groups, a transmission gate group. A transmission gate is selected from the selected transmission gate group. Finally, a data signal associated with the selected transmission gate is provided at an output of the multiplexer.
摘要翻译：用于操作多路复用器的技术包括从多个传输门组选择传输门组。从选择的传输门组中选择传输门。最后，在多路复用器的输出处提供与选择的传输门相关联的数据信号。

7. 发明申请

US20080082882A1 DOUBLE-EDGE TRIGGERED SCANNABLE PULSED FLIP-FLOP FOR HIGH FREQUENCY AND/OR LOW POWER APPLICATIONS 审中-公开
标题翻译：用于高频和/或低功率应用的双边触发扫描脉冲FLIP-FLOP
公开(公告)号：US20080082882A1
公开(公告)日：2008-04-03
申请号：US11531310
申请日：2006-09-13
申请人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
发明人： Christopher M. Durham , Jenny Fan , Peter J. Klim , Robert N. Krentler
IPC分类号： G01R31/28
CPC分类号： G01R31/318575 , G01R31/318502 , G01R31/318541
摘要： A circuit for data storage is presented. The circuit includes clock generation circuits for generating a pulse clock signal having first and second clock pulses for each clock cycle of a system clock and first and second scan clock signals. The circuit further includes a scannable pulse flip-flop circuit having a data input and a data output that are connected with an internal storage node, and a scan input and a scan output that are also connected with the internal storage node. In a function mode of operation, the first and second scan clock signals are held at a logic level to allow data to pass from the data input to the internal storage node at the first clock pulse and from the internal storage node to the data output at the second clock pulse signal. In a scan mode of operation the pulse clock signal is held at a logic level to allow data to pass from the scan input to the internal storage node at a pulse of the first scan clock signal and from the internal storage node to the scan output at a pulse of the second scan clock signal.
摘要翻译：介绍了一种用于数据存储的电路。电路包括用于产生具有用于系统时钟的每个时钟周期的第一和第二时钟脉冲和第一和第二扫描时钟信号的脉冲时钟信号的时钟产生电路。电路还包括具有与内部存储节点连接的数据输入和数据输出以及也与内部存储节点连接的扫描输入和扫描输出的可扫描脉冲触发器电路。在功能操作模式中，第一和第二扫描时钟信号被保持在逻辑电平，以允许数据在第一时钟脉冲从数据输入到内部存储节点并从内部存储节点传递到数据输出第二个时钟脉冲信号。在扫描操作模式中，脉冲时钟信号保持在逻辑电平，以允许数据以第一扫描时钟信号的脉冲从扫描输入传递到内部存储节点，并且从内部存储节点到扫描输出第二扫描时钟信号的脉冲。

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