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1. 发明授权

US08092734B2 Covers for microelectronic imagers and methods for wafer-level packaging of microelectronics imagers 有权
标题翻译：用于微电子成像器的封装以及用于微电子成像器的晶片级封装的方法
公开(公告)号：US08092734B2
公开(公告)日：2012-01-10
申请号：US10845304
申请日：2004-05-13
申请人： Tongbi Jiang , J. Mike Brooks
发明人： Tongbi Jiang , J. Mike Brooks
IPC分类号： B29C65/00
CPC分类号： H01L31/0203 , B33Y80/00 , H01L27/14618 , H01L27/14625 , H01L31/02325 , H01L2224/48227 , H04N5/2253 , H04N5/2254 , H01L2224/48091 , H01L2924/00014
摘要： Methods for forming and attaching covers to microelectronic imaging units, packaging microelectronic imagers at the wafer level, and microelectronic imagers having covers that protect the image sensor are disclosed herein. In one embodiment, a method includes providing a first substrate having a plurality of covers, the covers including windows comprising regions of the first substrate and stand-offs projecting from the windows. The method continues by providing a second substrate having a plurality of microelectronic dies with image sensors, integrated circuits electrically coupled to the image sensors, and terminals electrically coupled to the integrated circuits. The method includes assembling the covers with corresponding dies so that the windows are aligned with corresponding image sensors and stand-offs contact corresponding dies inboard of the terminals and outboard of the image sensors. The first substrate is then cut to singulate the individual covers, after which the second substrate is cut to singulate individual imaging units.
摘要翻译：本文公开了用于在微晶电子成像单元上形成和附着盖子，在晶片级封装微电子成像器的方法以及具有保护图像传感器的覆盖物的微电子成像器。在一个实施例中，一种方法包括提供具有多个盖的第一基板，所述盖包括包括第一基板的区域和从窗口突出的支架的窗口。该方法继续通过提供具有多个具有图像传感器的多个微电子管芯的第二基板，电耦合到图像传感器的集成电路和电耦合到集成电路的端子。该方法包括将盖与相应的模具进行组装，使得窗口与对应的图像传感器对准，并且支架将接触端子和图像传感器外侧的对应的模具接触。然后切割第一衬底以分离单个覆盖物，然后将第二衬底切割成单个成像单元。

2. 发明授权

US06362532B1 Semiconductor device having ball-bonded pads 失效
标题翻译：具有球形焊盘的半导体器件
公开(公告)号：US06362532B1
公开(公告)日：2002-03-26
申请号：US09536965
申请日：2000-03-28
申请人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
发明人： J. Mike Brooks , Alan G. Wood , Kevin G. Duesman
IPC分类号： H01L2328
CPC分类号： H01L23/3107 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L24/81 , H01L29/0657 , H01L2224/11 , H01L2224/1134 , H01L2224/1191 , H01L2224/13 , H01L2224/1308 , H01L2224/13124 , H01L2224/13144 , H01L2224/13164 , H01L2224/16 , H01L2224/274 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/81801 , H01L2224/94 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01046 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10157 , H01L2924/12042 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2224/13099 , H01L2924/00 , H01L2924/00012 , H01L2224/03
摘要： A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.
摘要翻译：一种用于形成半导体器件的方法包括以下步骤：提供其上具有多个焊盘的半导体管芯，其中至少一个接合线与所述焊盘中的一个电连接并提供其中具有空腔的保持器。将模具放置在空腔中，然后在空腔内形成一层封装以覆盖模具。随后，将封装的模头从空腔中取出。

3. 发明授权

US5583372A Adhesion enhanced semiconductor die for mold compound packaging 失效
标题翻译：粘合增强半导体模具用于模具复合包装
公开(公告)号：US5583372A
公开(公告)日：1996-12-10
申请号：US306024
申请日：1994-09-14
申请人： Jerrold L. King , J. Mike Brooks , Walter L. Moden
发明人： Jerrold L. King , J. Mike Brooks , Walter L. Moden
IPC分类号： H01L23/31 , H01L23/495 , H01L23/12 , H01L23/482
CPC分类号： H01L23/4951 , H01L23/3142 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L24/48 , H01L2924/00014 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1815
摘要： A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces delamination potential of the die from the package.
摘要翻译：半导体管芯包括沉积在其上的金属层，用于增强管芯和模具复合封装之间的附着力。金属层基本上不含氧化物。通过电镀或无电涂覆技术将模具涂覆有一层或多层铜（Cu）和/或钯（Pd）。金属层提供均匀的润湿表面，用于在封装期间模具与模具化合物的更好粘合。增加的粘附力降低了模具从包装中的分层势。

4. 发明授权

US07312101B2 Packaged microelectronic devices and methods for packaging microelectronic devices 有权
标题翻译：用于封装微电子器件的封装的微电子器件和方法
公开(公告)号：US07312101B2
公开(公告)日：2007-12-25
申请号：US10421452
申请日：2003-04-22
申请人： Tongbi Jiang , J. Mike Brooks
发明人： Tongbi Jiang , J. Mike Brooks
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L21/20
CPC分类号： H01L24/19 , H01L23/5389 , H01L24/24 , H01L24/83 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/24227 , H01L2224/32245 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/83192 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/351 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.
摘要翻译：封装的微电子器件和用于封装微电子器件的方法在本文中公开。在一个实施例中，包括微电子器件的方法包括具有多个接合焊盘的第一侧的微电子管芯和与第一侧相对的第二侧的微电子器件包括在衬底中形成凹槽，将微电子管芯置于形成的凹部中在具有第二面朝向衬底的衬底中，并且在将微电子管芯放置在凹槽中之后用介电层覆盖微电子管芯的第一侧。衬底可以包括导热衬底，例如由铜和/或铝构成的衬底。衬底可以具有至少近似等于微电子管芯或印刷电路板的热膨胀系数的热膨胀系数。

5. 发明授权

US06600215B1 Method and apparatus for coupling a semiconductor die to die terminals 失效
公开(公告)号：US06600215B1
公开(公告)日：2003-07-29
申请号：US09054275
申请日：1998-04-02
申请人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
发明人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49838 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49433 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012
摘要： A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

6. 发明授权

US6066514A Adhesion enhanced semiconductor die for mold compound packaging 失效
公开(公告)号：US6066514A
公开(公告)日：2000-05-23
申请号：US963395
申请日：1997-11-03
申请人： Jerrold L. King , J. Mike Brooks , Walter L. Moden
发明人： Jerrold L. King , J. Mike Brooks , Walter L. Moden
IPC分类号： H01L23/31 , H01L23/495 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L23/3142 , H01L23/4951 , H01L2224/05599 , H01L2224/32014 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L2224/85399 , H01L24/48 , H01L2924/00014 , H01L2924/0102 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/10253 , H01L2924/14 , H01L2924/1532 , H01L2924/1815 , Y10S438/926 , Y10S438/928
摘要： A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces the delamination potential of the die from the package.

7. 发明授权

US6060343A Method of forming an integrated circuit device having cyanate ester buffer coat 有权
公开(公告)号：US6060343A
公开(公告)日：2000-05-09
申请号：US257402
申请日：1999-02-25
申请人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
发明人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
IPC分类号： H01L21/56 , H01L23/29 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L21/56 , H01L23/293 , H01L2224/274 , H01L2224/48091 , H01L2224/73265 , H01L2224/854 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , Y10S438/902 , Y10T29/49146 , Y10T29/49171
摘要： An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.

8. 发明授权

US5903046A Integrated circuit device having cyanate ester buffer coat 失效
标题翻译：具有氰酸酯缓冲层的集成电路装置
公开(公告)号：US5903046A
公开(公告)日：1999-05-11
申请号：US604219
申请日：1996-02-20
申请人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
发明人： J. Mike Brooks , Jerrold L. King , Kevin Schofield
IPC分类号： H01L21/56 , H01L23/29 , H01L23/28 , G03F7/0249
CPC分类号： H01L21/56 , H01L23/293 , H01L2224/274 , H01L2224/48091 , H01L2224/73265 , H01L2224/854 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/12042 , H01L2924/14 , Y10S438/902 , Y10T29/49146 , Y10T29/49171
摘要： An integrated circuit including a fabricated die having a cyanate ester buffer coating material thereon. The cyanate ester buffer coating material includes one or more openings for access to the die. A package device may be connected to the die bond pads through such openings. Further, an integrated circuit device is provided that includes a fabricated wafer including a plurality of integrated circuits fabricated thereon. The fabricated wafer has an upper surface with a cyanate ester buffer coating material cured on the upper surface of the fabricated integrated circuit device. Further, a method of producing an integrated circuit device includes providing a fabricated wafer including a plurality of integrated circuits and applying a cyanate ester coating material on a surface of the fabricated wafer. The application of cyanate ester coating material may include spinning the cyanate ester coating material on the surface of the fabricated wafer to form a buffer coat.
摘要翻译：一种集成电路，包括其上具有氰酸酯缓冲涂层材料的制造的模具。氰酸酯缓冲涂料包括用于进入模具的一个或多个开口。封装器件可以通过这样的开口连接到管芯接合焊盘。此外，提供一种集成电路器件，其包括制造在其上的多个集成电路的制造晶片。制造的晶片具有在制造的集成电路器件的上表面上固化的氰酸酯缓冲涂层材料的上表面。此外，制造集成电路器件的方法包括提供包括多个集成电路的制造晶片，并在制造晶片的表面上施加氰酸酯涂层材料。氰酸酯涂料的应用可以包括在制造的晶片的表面上旋转氰酸酯涂料以形成缓冲涂层。

9. 发明申请

US20080132006A1 PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR PACKAGING MICROELECTRONIC DEVICES 有权
公开(公告)号：US20080132006A1
公开(公告)日：2008-06-05
申请号：US12028211
申请日：2008-02-08
申请人： Tongbi Jiang , J. Mike Brooks
发明人： Tongbi Jiang , J. Mike Brooks
IPC分类号： H01L21/00
CPC分类号： H01L24/19 , H01L23/5389 , H01L24/24 , H01L24/83 , H01L24/97 , H01L2224/04105 , H01L2224/12105 , H01L2224/20 , H01L2224/24227 , H01L2224/32245 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/83192 , H01L2224/92244 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15747 , H01L2924/181 , H01L2924/351 , H01L2224/82 , H01L2924/00 , H01L2224/83
摘要： Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

10. 发明授权

US5760468A Adhesion enhanced semiconductor die for mold compound packaging 失效
标题翻译：粘合增强半导体模具用于模具复合包装
公开(公告)号：US5760468A
公开(公告)日：1998-06-02
申请号：US731793
申请日：1996-10-18
申请人： Jerrold L. King , J. Mike Brooks , Walter L. Moden
发明人： Jerrold L. King , J. Mike Brooks , Walter L. Moden
IPC分类号： H01L23/31 , H01L23/495 , H01L23/48 , H01L23/52
CPC分类号： H01L23/4951 , H01L23/3142 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/73215 , H01L24/48 , H01L2924/00014 , H01L2924/01046 , H01L2924/10253 , H01L2924/14 , H01L2924/1815
摘要： A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces delamination potential of the die from the package.
摘要翻译：半导体管芯包括沉积在其上的金属层，用于增强管芯和模具复合封装之间的附着力。金属层基本上不含氧化物。通过电镀或无电涂覆技术将模具涂覆有一层或多层铜（Cu）和/或钯（Pd）。金属层提供均匀的润湿表面，用于在包封期间模具与模具复合包装的更好的附着。增加的粘附力降低了模具从包装中的分层势。

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