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1. 发明授权

US07253064B2 Cascode I/O driver with improved ESD operation 有权
标题翻译：串行I / O驱动器，具有改进的ESD操作
公开(公告)号：US07253064B2
公开(公告)日：2007-08-07
申请号：US10853538
申请日：2004-05-25
申请人： Michael D. Chaine , Manny K. F. Ma
发明人： Michael D. Chaine , Manny K. F. Ma
IPC分类号： H01L21/336
CPC分类号： H01L29/7831 , H01L27/0266 , H01L29/0649 , H01L29/0692 , H01L29/41725
摘要： A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.
摘要翻译：描述了包括形成在两个晶体管之间的共享区域中的屏障的级联I / O驱动器。屏障区域允许I / O驱动程序设计为主要满足I / O要求。因此，实现了改进的操作速度。描述了包括与ESD装置并联的I / O驱动器的系统。在一个实施例中，在ESD开始导通之后，I / O驱动器可以辅助静电装置放电静电。

2. 发明授权

US06600215B1 Method and apparatus for coupling a semiconductor die to die terminals 失效
公开(公告)号：US06600215B1
公开(公告)日：2003-07-29
申请号：US09054275
申请日：1998-04-02
申请人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
发明人： Aaron Schoenfeld , Manny K. F. Ma , Larry D. Kinsman , J. Mike Brooks , Timothy J. Allen
IPC分类号： H01L2348
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/49838 , H01L23/642 , H01L23/645 , H01L24/45 , H01L24/48 , H01L24/49 , H01L2224/04042 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/06136 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49433 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01079 , H01L2924/014 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H01L2924/00 , H01L2924/00012
摘要： A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals. The first and second conductive members may each have an intermediate portion between the first and second end portions thereof that is narrower than the second end portions thereof, and the conductive members may be staggered by axially offsetting the second end portion of the second conductive member from the second end portion of the first conductive member.

3. 发明授权

US6069492A Voltage compensating CMOS input buffer circuit 失效
标题翻译：电压补偿CMOS输入缓冲电路
公开(公告)号：US6069492A
公开(公告)日：2000-05-30
申请号：US925376
申请日：1997-09-08
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K19/003 , H03K19/0185 , H03K17/0185
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.
摘要翻译：电压补偿CMOS输入缓冲器将输入TTL信号转换为CMOS逻辑电平，并通过使用n沟道晶体管来补偿变化的电源电压，从而将p沟道对的有效尺寸比改变成组成输入反相器的n沟道晶体管。补偿晶体管可以以增加的电源电压工作，以帮助n沟道输入反相器晶体管偏移通过增加电源电压而其跳变点将被增加的p沟道输入反相器晶体管。随着电源电压的降低，补偿晶体管关闭，使输入逆变器返回原来的大小比例。补偿晶体管的栅极通过两个二极管耦合到电源电压，以控制流过补偿晶体管的电流量。与补偿晶体管串联的另外的跳变点晶体管的栅极耦合到输入信号以帮助稳定跳变点。输出级反相器从输入反相器的输出提供CMOS逻辑电平。

4. 发明授权

US6011386A Frequency adjustable, zero temperature coefficient referencing ring oscillator circuit 失效
标题翻译：频率可调，零温度系数参考环形振荡器电路
公开(公告)号：US6011386A
公开(公告)日：2000-01-04
申请号：US911897
申请日：1997-08-15
申请人： Wen Li , Manny K. F. Ma
发明人： Wen Li , Manny K. F. Ma
IPC分类号： G05F3/24 , G05F3/26 , G05F3/08
CPC分类号： G05F3/262 , G05F3/242
摘要： A frequency adjustable, zero temperature coefficient referencing ring oscillator circuit includes a plurality of inverter stages each having a switching circuit that produces the oscillating output signal for the ring oscillator circuit and a control circuit that controls the switching circuit to establish the frequency of the output signal, the control circuit including field-effect transistors which are operated as output resistance controllable devices and which have their operating points, and thus their output resistances, established by a reference voltage that is produced by a precision reference voltage generating circuit so that the operating frequency of the ring oscillator circuit can be set by adjusting the value of the reference signals produced by the precision reference signal generating circuit and is maintained at the setpoint value because the precision reference voltage generating circuit operates independently of variations in temperature and/or the power supply voltage. The ring oscillator circuit is fabricated as an integrated circuit device and the operating frequency of the integrated circuit ring oscillator circuit can be adjusted after fabrication and passivation of the integrated circuit device.
摘要翻译：频率可调，零温度系数参考环形振荡器电路包括多个反相器级，每个反相器级具有产生环形振荡器电路的振荡输出信号的开关电路和控制开关电路以建立输出信号频率的控制电路所述控制电路包括作为输出电阻可控设备操作并具有其工作点的场效应晶体管，并且因此其输出电阻由由精密参考电压发生电路产生的参考电压建立，使得工作频率可以通过调整精密基准信号发生电路产生的参考信号的值来设置环形振荡器电路，并且由于精密基准电压产生电路独立于温度和/或电源的变化而运行，因此保持在设定值卷天气好环形振荡器电路被制造为集成电路器件，并且集成电路环形振荡器电路的工作频率可以在集成电路器件的制造和钝化之后被调整。

5. 发明授权

US5744839A ESD protection using selective siliciding techniques 失效
公开(公告)号：US5744839A
公开(公告)日：1998-04-28
申请号：US661447
申请日：1996-06-11
申请人： Manny K. F. Ma , Aaron Schoenfeld
发明人： Manny K. F. Ma , Aaron Schoenfeld
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0251
摘要： The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined discharge paths are created for discharging input and output buffer pads, during an ESD event, through ESD protection devices. During fabrication, an oxide layer is utilized as a mask to prevent silicided regions from forming in source/drain regions, self-aligned with the gates. The buffer transistor gate-to-contact spacing is made longer than the gate-to-contact spacing in the associated protection transistor, to shunt charge through the protection device. In a further embodiment, active area resistance is formed between the output/input buffer transistor and the ESD protection device, to further increase the resistance of the path between the buffer pad to the associated buffer transistor.

6. 发明授权

US5578941A Voltage compensating CMOS input buffer circuit 失效
公开(公告)号：US5578941A
公开(公告)日：1996-11-26
申请号：US518546
申请日：1995-08-23
申请人： Joseph C. Sher , Manny K. F. Ma
发明人： Joseph C. Sher , Manny K. F. Ma
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0948
CPC分类号： H03K19/018521 , H03K19/00384
摘要： A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points. An output stage inverter provides the CMOS logic levels from the output of the input inverter.

7. 发明授权

US6055193A Charge pump circuits and devices containing such 有权
标题翻译：电荷泵电路和包含此类的装置
公开(公告)号：US6055193A
公开(公告)日：2000-04-25
申请号：US348808
申请日：1999-07-07
申请人： Troy A. Manning , Manny K. F. Ma
发明人： Troy A. Manning , Manny K. F. Ma
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00
CPC分类号： G11C5/146 , G11C11/4074
摘要： Circuits to convert an input voltage supply to an output voltage supply having a different magnitude or polarity. The circuits include a capacitor having a first terminal and a second terminal, a first switch coupled to the first terminal of the capacitor, and a second switch. The circuits further include a first node coupled between the second terminal of the capacitor and the second switch, and a third switch having a first terminal coupled to the first node and a second terminal coupled to a second node. The first switch is adapted to couple the first terminal of the capacitor to the input supply voltage during a fill state and a second voltage level during a dump state. The second switch is adapted to couple the first node to a third voltage level during the fill state and present a high impedance to the first node during the dump state. The third switch is adapted to dump a charge from the first node to the second node during the dump state, thereby producing an output voltage at the second node.
摘要翻译：将输入电压源转换为具有不同大小或极性的输出电压源的电路。电路包括具有第一端子和第二端子的电容器，耦合到电容器的第一端子的第一开关和第二开关。电路还包括耦合在电容器的第二端子和第二开关之间的第一节点和具有耦合到第一节点的第一端子的第三开关和耦合到第二节点的第二端子。第一开关适于在充电状态期间将电容器的第一端子耦合到输入电源电压，并且在转储状态期间将第二电压电平耦合到第二电压电平。第二开关适于在填充状态期间将第一节点耦合到第三电压电平，并且在转储状态期间向第一节点呈现高阻抗。第三开关适于在转储状态期间将电荷从第一节点转储到第二节点，从而在第二节点产生输出电压。

8. 发明授权

US6022787A Method of making a structure for providing signal isolation and decoupling in an integrated circuit device 失效
标题翻译：制造用于在集成电路器件中提供信号隔离和去耦的结构的方法
公开(公告)号：US6022787A
公开(公告)日：2000-02-08
申请号：US847275
申请日：1997-05-01
申请人： Manny K. F. Ma
发明人： Manny K. F. Ma
IPC分类号： H01L23/522 , H01L21/76
CPC分类号： H01L23/5222 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903
摘要： A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric material and enclosed within an isolation structure of an electrically conductive material which is formed in the integrated circuit device and extends substantially the length of the conductor, the isolation structure including top and bottom walls of electrically conductive material and first and side walls, also of an electrically conductive material, which electrically interconnect the top and bottom walls, forming an enclosure around the conductor. Also described is a method for fabricating the isolation structure in the integrated circuit device.
摘要翻译：在集成电路器件中制造的用于为集成电路器件的信号承载导体提供信号隔离和去耦的信号隔离和去耦结构，其中一个导体被嵌入电介质材料中并封装在导电材料的隔离结构内，形成在集成电路器件中并且基本上延伸导体的长度，隔离结构包括导电材料的顶壁和底壁以及电导体互连顶壁和底壁的导电材料的第一侧壁和侧壁，形成围绕导体的外壳。还描述了一种用于在集成电路器件中制造隔离结构的方法。

9. 发明授权

US5982599A Input/output electrostatic discharge protection for devices with multiple individual power groups 失效
标题翻译：具有多个独立电源组的设备的输入/输出静电放电保护
公开(公告)号：US5982599A
公开(公告)日：1999-11-09
申请号：US961341
申请日：1997-10-30
申请人： Manny K. F. Ma , Jeffrey P. Wright
发明人： Manny K. F. Ma , Jeffrey P. Wright
IPC分类号： H02H9/04 , H02H3/22
CPC分类号： H02H9/046
摘要： An electrostatic discharge protection system for an integrated circuit device, such as a solid state memory device or any other integrated circuit device having a plurality of individual power groups, includes a loop of an electrically conductive material that is disposed on the device defining a electrostatic discharge path portion, a plurality of first punch-through devices which connect the input/output pins of different power groups of the integrated circuit device to the power sources of the associated power group, and a plurality of second punch-through devices which connect all of the input/output pins of the integrated circuit device to the electrostatic discharge path portion, thereby providing a discharge path that is common to all of the power groups of the integrated circuit device.
摘要翻译：用于集成电路装置的静电放电保护系统，例如固体存储装置或具有多个单独功率组的任何其它集成电路装置，包括导电材料的环，该环路设置在限定静电放电多个第一穿通装置，其将集成电路装置的不同功率组的输入/输出引脚连接到相关联的电力组的电源;以及多个第二穿通装置，其将所有集成电路装置的输入/输出引脚连接到静电放电路径部分，从而提供对集成电路装置的所有功率组共同的放电路径。

10. 发明授权

US5946259A Voltage generator methods and apparatus 有权
标题翻译：电压发生器的方法和装置
公开(公告)号：US5946259A
公开(公告)日：1999-08-31
申请号：US144736
申请日：1998-09-01
申请人： Troy A. Manning , Manny K. F. Ma
发明人： Troy A. Manning , Manny K. F. Ma
IPC分类号： G11C5/14 , G11C11/4074 , G11C7/00 , G11C16/04
CPC分类号： G11C5/146 , G11C11/4074
摘要： A reduced threshold voltage (Vt) magnitude or depletion mode metal-oxide-semiconductor (MOS) capacitor capable of use in a charge pump circuit such as a substrate bias voltage generator in a dynamic random access memory (DRAM) integrated circuit. The Vt magnitude of a p-channel MOS field-effect transistor (FET) used as a capacitor is reduced by using the same ion-implantation step used to increase the Vt magnitude of an n-channel MOS FET. The Vt magnitude of an n-channel MOS FET used as a capacitor is reduced by using the same ion-implantation step used to increase the Vt magnitude of a p-channel MOS FET. By sufficiently reducing Vt magnitude, a depletion mode MOS capacitor is formed. Reduced Vt magnitude and depletion mode MOS capacitors increase the useful voltage range of the capacitor, optimizing operation at low supply voltages.
摘要翻译：能够用于诸如动态随机存取存储器（DRAM）集成电路中的衬底偏置电压发生器的电荷泵电路中的降低阈值电压（Vt）幅度或耗尽型金属氧化物半导体（MOS）电容器。通过使用用于增加n沟道MOS FET的Vt幅度的相同的离子注入步骤来减小用作电容器的p沟道MOS场效应晶体管（FET）的Vt幅度。用作电容器的n沟道MOS FET的Vt大小通过使用用于增加p沟道MOS FET的Vt幅度的相同的离子注入步骤来减小。通过充分降低Vt幅度，形成耗尽型MOS电容器。降低Vt幅度和耗尽模式MOS电容器增加了电容器的有用电压范围，优化了低电源电压下的工作。

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