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    • 1. 发明申请
    • METHODS OF MANUFACTURING PHASE-CHANGE MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    • 制造相变存储器件和半导体器件的方法
    • US20130102120A1
    • 2013-04-25
    • US13339891
    • 2011-12-29
    • Hye Jin SeoKeum Bum Lee
    • Hye Jin SeoKeum Bum Lee
    • H01L21/62
    • H01L45/06H01L27/2409H01L45/126H01L45/1608H01L45/1683
    • Methods of manufacturing a phase-change memory device and a semiconductor device are provided. The method of manufacturing the phase-change memory device includes forming a switching device layer, an ohmic contact layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer to form a hard mask pattern, etching the ohmic layer and the switching layer using the hard mask pattern to form a pattern structure including an ohmic contact pattern, a switching device pattern, and the hard mask pattern, selectively oxidizing a surface of the pattern structure, forming an insulating layer to bury the pattern structure, and selectively removing the hard mask pattern other than the oxidized surface thereof to form a contact hole.
    • 提供了制造相变存储器件和半导体器件的方法。 制造相变存储器件的方法包括在半导体衬底上形成开关器件层,欧姆接触层和硬掩模层,图案化硬掩模层以形成硬掩模图案,蚀刻欧姆层和 使用硬掩模图案形成包括欧姆接触图案,开关器件图案和硬掩模图案的图案结构的切换层,选择性地氧化图案结构的表面,形成绝缘层以埋藏图案结构,并且选择性地 除去其氧化表面以外的硬掩模图案以形成接触孔。
    • 8. 发明申请
    • Methods for forming dual poly gate of semiconductor device
    • 用于形成半导体器件双重多晶硅栅极的方法
    • US20080003751A1
    • 2008-01-03
    • US11646730
    • 2006-12-28
    • Cheol Hwan ParkDong Su ParkEun A. LeeHye Jin Seo
    • Cheol Hwan ParkDong Su ParkEun A. LeeHye Jin Seo
    • H01L21/336
    • H01L21/82345H01L21/28044H01L21/324H01L21/823842
    • A method for forming a dual poly gate of a semiconductor device includes forming a gate insulating layer on a semiconductor substrate having a first region and a second region; forming an amorphous silicon layer, in which a portion defined by the first region is implanted with impurity ions of a first conductivity type and a portion defined by the second region is implanted with impurity ions of a second conductivity type, on the gate insulating layer; forming silicon seeds on the amorphous silicon layer; forming hemispherical grains on the surface of the amorphous silicon layer using the silicon seeds; and activating the implanted impurity ions and crystallizing the amorphous silicon layer having the hemispherical grains formed thereon by annealing to form a polysilicon layer of a first conductivity type and a polysilicon layer of a second conductivity type in the portions of the amorphous silicon layer defined by the first and second regions, respectively.
    • 一种用于形成半导体器件的双多晶硅栅极的方法包括在具有第一区域和第二区域的半导体衬底上形成栅极绝缘层; 形成非晶硅层,其中由栅极绝缘层注入由第一导电类型的杂质离子和由第二区限定的部分,由第一区限定的部分注入第二导电类型的杂质离子; 在所述非晶硅层上形成硅晶种; 使用硅晶粒在非晶硅层的表面上形成半球状晶粒; 并激活注入的杂质离子并使其上形成有半球形晶粒的非晶硅层通过退火结晶,以在由非晶硅层限定的部分中形成第一导电类型的多晶硅层和第二导电类型的多晶硅层 第一和第二区域。