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1. 发明授权

US08097912B2 Systems and methods for self convergence during erase of a non-volatile memory device 有权
标题翻译：用于在非易失性存储器件擦除期间自会聚的系统和方法
公开(公告)号：US08097912B2
公开(公告)日：2012-01-17
申请号：US11762677
申请日：2007-06-13
申请人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
发明人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/115 , G11C16/3404 , G11C16/3409 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.
摘要翻译：非易失性存储器件通过控制栅极结构中的电介质层以及整个栅极结构的物理方面，例如厚度，宽度，面积等来在正常擦除周期期间实现自会聚。还可以在正常擦除周期期间通过在擦除周期期间斜坡施加到控制栅极的擦除电压来辅助自会聚。

2. 发明申请

US20050040467A1 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US20050040467A1
公开(公告)日：2005-02-24
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/8247 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

3. 发明授权

US06177317B1 Method of making nonvolatile memory devices having reduced resistance diffusion regions 有权
标题翻译：制造具有减小的电阻扩散区域的非易失性存储器件的方法
公开(公告)号：US06177317B1
公开(公告)日：2001-01-23
申请号：US09291915
申请日：1999-04-14
申请人： Chin-Yi Huang , Huei Huarng Chen , Yun Chang , Samuel C. Pan
发明人： Chin-Yi Huang , Huei Huarng Chen , Yun Chang , Samuel C. Pan
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.
摘要翻译：描述了一种用于制造具有减小的电阻扩散区域的非易失性存储器件的方法。该方法的一个实施例包括在包括隧道氧化物层，多晶硅层和蚀刻停止层的衬底上形成多层结构。在多层结构上执行光致抗蚀剂掩模处理以限定非易失性存储器件的栅极。然后沉积间隔层并回蚀刻以形成邻近栅极的侧壁间隔物。侧壁间隔物的宽度用于限定源极和漏极区域的宽度以及栅极之间的沟槽的宽度。使用高选择性蚀刻形成沟槽，其蚀刻通过衬底比侧壁间隔物和蚀刻停止层更快。在器件的区域上形成导电层并进行蚀刻以形成减小的电阻扩散区域和所需的沟槽结构。然后用绝缘材料填充沟槽。

4. 发明授权

US07005696B2 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US07005696B2
公开(公告)日：2006-02-28
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

5. 发明申请

US20050006795A1 Corner free structure of nonvolatile memory 审中-公开
标题翻译：非易失性存储器的无角结构
公开(公告)号：US20050006795A1
公开(公告)日：2005-01-13
申请号：US10614892
申请日：2003-07-09
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hong-Chi Chen
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hong-Chi Chen
IPC分类号： H01L21/336 , H01L27/108 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/42324 , H01L29/7883
摘要： A corner free structure of a nonvolatile memory is disclosed in this present invention. The key aspect of this present invention is employing a corner free structure for isolating a trench isolation device and a nonvolatile memory, and thus the reliability of the above-mentioned nonvolatile memory is improved. Furthermore, based on the definition of coupling ratio, as a result of the above-cited corner free structure, the effective channel area of the nonvolatile memory is modified, and thus the nonvolatile memory according to this present invention can achieve higher efficiency than the nonvolatile memory in the prior art. Therefore, this invention can not only improve the reliability of a nonvolatile memory, but also advance the efficiency of the nonvolatile memory.
摘要翻译：在本发明中公开了非易失性存储器的无角结构。本发明的关键方面是采用无角结构来隔离沟槽隔离装置和非易失性存储器，从而提高了上述非易失性存储器的可靠性。此外，基于耦合比的定义，作为上述无角结构的结果，非易失性存储器的有效沟道面积被修改，因此根据本发明的非易失性存储器可以实现比非易失性存储器更高的效率现有技术中的记忆。因此，本发明不仅可以提高非易失性存储器的可靠性，而且可以提高非易失性存储器的效率。

6. 发明授权

US07384848B2 Method for forming non-volatile memory with inlaid floating gate 有权
标题翻译：用镶嵌浮动门形成非易失性存储器的方法
公开(公告)号：US07384848B2
公开(公告)日：2008-06-10
申请号：US11281928
申请日：2005-11-18
申请人： Chun-Pei Wu , Wei-Ming Chung , Huei-Huarng Chen
发明人： Chun-Pei Wu , Wei-Ming Chung , Huei-Huarng Chen
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is formed over the substrate and the second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. Then a shallow trench isolation is formed into the expose the buried diffusion region and the substrate. Next a floating gate pattern is transferred into the first and second dielectric layers. Next the first dielectric layer is removed to expose the pad dielectric layer. Then the exposed pad dielectric layer is removed to expose the substrate. Next a tunnel dielectric layer is formed on the exposed substrate. Next a first conductive layer is conformally formed over the substrate and is planarized to expose the shallow trench isolation. Then an inter gate dielectric layer is formed over the first conductive layer and the shallow trench isolation. Finally a second conductive layer is formed over the inter gate dielectric layer.
摘要翻译：公开了一种用嵌入式浮动栅极形成非易失性存储器的方法。该方法包括以下步骤。提供了具有焊盘电介质层和其上的第一电介质层的衬底。然后在衬底中形成掩埋扩散区。接下来，在衬底上形成第二电介质层，然后将第二电介质层和焊盘电介质层回蚀刻以暴露掩埋扩散区域和第一介电层。然后形成浅沟槽隔离，将掩埋的扩散区域和衬底暴露。接下来，浮置栅极图案被转移到第一和第二电介质层中。接下来，去除第一介电层以露出焊盘介电层。然后去除暴露的焊盘介电层以露出衬底。接下来，在暴露的基板上形成隧道介电层。接下来，第一导电层保形地形成在衬底上并且被平坦化以暴露浅沟槽隔离。然后在第一导电层和浅沟槽隔离件之上形成栅极介电层。最后，在栅极间介电层上形成第二导电层。

7. 发明授权

US06821841B1 Method for fabricating a mask read-only-memory with diode cells 有权
标题翻译：用二极管电池制造掩膜只读存储器的方法
公开(公告)号：US06821841B1
公开(公告)日：2004-11-23
申请号：US10643964
申请日：2003-08-20
申请人： Chun-Pei Wu , Huei-Huarng Chen , Wen-Bin Tsai , Hsuan-Ling Kao
发明人： Chun-Pei Wu , Huei-Huarng Chen , Wen-Bin Tsai , Hsuan-Ling Kao
IPC分类号： H01L218242
CPC分类号： H01L27/112 , H01L27/11253 , H01L27/1126
摘要： A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.
摘要翻译：提供了一种制造具有二极管单元的掩模只读存储器的方法。在位线上形成具有第一导电性的掺杂导电层。然后，在用作蚀刻掩模的掺杂导电层上的层间电介质层上形成具有掩模ROM图案的光致抗蚀剂层，从而在层间电介质层中向掺杂导电层的暴露区域形成开口。进行离子注入以形成具有与掺杂导电层的每个暴露区域中的第一导电性相反的第二导电性的扩散区域，使得在其中形成的掺杂导电层和扩散区域构成用作存储单元的二极管单元。在二极管单元的每个开口中形成接触塞，并且在接触插塞上形成用作字线的导电层。

8. 发明申请

US20080308857A1 Systems and Methods for Self Convergence During Erase of a Non-Volatile Memory Device 有权
标题翻译：擦除非易失性存储器件期间自收敛的系统和方法
公开(公告)号：US20080308857A1
公开(公告)日：2008-12-18
申请号：US11762677
申请日：2007-06-13
申请人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
发明人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , G11C16/3404 , G11C16/3409 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.
摘要翻译：非易失性存储器件通过控制栅极结构中的电介质层以及整个栅极结构的物理方面，例如厚度，宽度，面积等来在正常擦除周期期间实现自会聚。还可以在正常擦除周期期间通过在擦除周期期间斜坡施加到控制栅极的擦除电压来辅助自会聚。

9. 发明授权

US07244661B2 Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate 有权
标题翻译：用于在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法
公开(公告)号：US07244661B2
公开(公告)日：2007-07-17
申请号：US11032045
申请日：2005-01-11
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.
摘要翻译：提供一种在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法。图案化的第一介电层形成在半导体衬底上用作第一硬掩模。进行热氧化处理以在半导体衬底的暴露的部分上形成场氧化物。然后去除图案化的第一介电层。在场氧化物和半导体衬底上形成用作第二硬掩模的第二图案化电介质层。执行各向同性蚀刻工艺以蚀刻场氧化物和半导体衬底的暴露部分。图案化的第二介电层和下面的场氧化物被去除以在半导体衬底的表面上形成多个沟槽。沿着半导体衬底中的沟槽的周围形成掩埋扩散层。

10. 发明申请

US20070117301A1 Method for forming non-volatile memory with inlaid floating gate 有权
标题翻译：用镶嵌浮动门形成非易失性存储器的方法
公开(公告)号：US20070117301A1
公开(公告)日：2007-05-24
申请号：US11281928
申请日：2005-11-18
申请人： Chun-Pei Wu , Wei-Ming Chung , Huei-Huarng Chen
发明人： Chun-Pei Wu , Wei-Ming Chung , Huei-Huarng Chen
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a non-volatile memory with inlaid floating gate is disclosed. The method comprises the following steps. A substrate having a pad dielectric layer and a first dielectric layer thereon is provided. Then a buried diffusion region is formed in the substrate. Next a second dielectric layer is formed over the substrate and the second dielectric layer and the pad dielectric layer are then etched back to expose the buried diffusion region and the first dielectric layer. Then a shallow trench isolation is formed into the expose the buried diffusion region and the substrate. Next a floating gate pattern is transferred into the first and second dielectric layers. Next the first dielectric layer is removed to expose the pad dielectric layer. Then the exposed pad dielectric layer is removed to expose the substrate. Next a tunnel dielectric layer is formed on the exposed substrate. Next a first conductive layer is conformally formed over the substrate and is planarized to expose the shallow trench isolation. Then an inter gate dielectric layer is formed over the first conductive layer and the shallow trench isolation. Finally a second conductive layer is formed over the inter gate dielectric layer.
摘要翻译：公开了一种用嵌入式浮动栅极形成非易失性存储器的方法。该方法包括以下步骤。提供了具有焊盘电介质层和其上的第一电介质层的衬底。然后在衬底中形成掩埋扩散区。接下来，在衬底上形成第二电介质层，然后将第二电介质层和焊盘电介质层回蚀刻以暴露掩埋扩散区域和第一介电层。然后形成浅沟槽隔离，将掩埋的扩散区域和衬底暴露。接下来，浮置栅极图案被转移到第一和第二电介质层中。接下来，去除第一介电层以露出焊盘介电层。然后去除暴露的焊盘介电层以露出衬底。接下来，在暴露的基板上形成隧道介电层。接下来，第一导电层保形地形成在衬底上并且被平坦化以暴露浅沟槽隔离。然后在第一导电层和浅沟槽隔离件之上形成栅极介电层。最后，在栅极间介电层上形成第二导电层。

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