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1. 发明授权

US07768825B2 Gated diode nonvolatile memory structure with diffusion barrier structure 有权
标题翻译：门极二极管非易失性存储器结构具有扩散阻挡结构
公开(公告)号：US07768825B2
公开(公告)日：2010-08-03
申请号：US11619108
申请日：2007-01-02
申请人： Hsuan Ling Kao , Wen Jer Tsai , Tien Fan Ou
发明人： Hsuan Ling Kao , Wen Jer Tsai , Tien Fan Ou
IPC分类号： G11C11/36
CPC分类号： H01L29/7391 , B82Y10/00 , G11C11/36 , H01L27/1021 , H01L27/11517 , H01L27/11568 , H01L29/8616 , Y10S977/938
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子和二极管节点之间的扩散阻挡结构的二极管结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

2. 发明授权

US07492638B2 Gated diode nonvolatile memory operation 有权
标题翻译：门极二极管非易失性存储器操作
公开(公告)号：US07492638B2
公开(公告)日：2009-02-17
申请号：US11619125
申请日：2007-01-02
申请人： Hsuan Ling Kao , Wen Jer Tsai , Tien Fan Ou , Yi Ying Liao
发明人： Hsuan Ling Kao , Wen Jer Tsai , Tien Fan Ou , Yi Ying Liao
IPC分类号： G11C11/34
CPC分类号： G11C11/39 , G11C11/5671 , G11C16/0466 , H01L27/1021 , H01L27/115 , H01L27/11568
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子和二极管节点之间的扩散阻挡结构的二极管结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

3. 发明授权

US07419868B2 Gated diode nonvolatile memory process 有权
标题翻译：门极二极管非易失性存储器工艺
公开(公告)号：US07419868B2
公开(公告)日：2008-09-02
申请号：US11619082
申请日：2007-01-02
申请人： Tien Fan Ou , Wen Jer Tsai , Erh-Kun Lai , Hsuan Ling Kao
发明人： Tien Fan Ou , Wen Jer Tsai , Erh-Kun Lai , Hsuan Ling Kao
IPC分类号： H01L21/8234
CPC分类号： H01L29/8616 , G11C16/02 , H01L27/1021 , H01L29/7391
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Various embodiments may include or exclude a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。各种实施例可以包括或排除二极管节点之间的扩散阻挡结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

4. 发明申请

US20080117677A1 Vertical Nonvolatile Memory Cell, Array, and Operation 有权
标题翻译：垂直非易失性存储单元，阵列和操作
公开(公告)号：US20080117677A1
公开(公告)日：2008-05-22
申请号：US11774452
申请日：2007-07-06
申请人： Tien Fan Ou , Wen Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
发明人： Tien Fan Ou , Wen Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0416 , G11C16/10 , H01L27/1026 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/7923 , H01L29/7926
摘要： A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的垂直非易失性存储单元包括具有三个节点的电荷控制结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

5. 发明申请

US20080117673A1 Gated Diode Nonvolatile Memory Operation 有权
标题翻译：门极二极管非易失性存储器操作
公开(公告)号：US20080117673A1
公开(公告)日：2008-05-22
申请号：US11619125
申请日：2007-01-02
申请人： Hsuan Ling Kao , Wen Jer Tsai , Tien Fan Ou , Yi Ying Liao
发明人： Hsuan Ling Kao , Wen Jer Tsai , Tien Fan Ou , Yi Ying Liao
IPC分类号： G11C11/36
CPC分类号： G11C11/39 , G11C11/5671 , G11C16/0466 , H01L27/1021 , H01L27/115 , H01L27/11568
摘要： A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal and a diffusion barrier structure between the diode nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子和二极管节点之间的扩散阻挡结构的二极管结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

6. 发明申请

US20050040467A1 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US20050040467A1
公开(公告)日：2005-02-24
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/8247 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

7. 发明授权

US06821841B1 Method for fabricating a mask read-only-memory with diode cells 有权
标题翻译：用二极管电池制造掩膜只读存储器的方法
公开(公告)号：US06821841B1
公开(公告)日：2004-11-23
申请号：US10643964
申请日：2003-08-20
申请人： Chun-Pei Wu , Huei-Huarng Chen , Wen-Bin Tsai , Hsuan-Ling Kao
发明人： Chun-Pei Wu , Huei-Huarng Chen , Wen-Bin Tsai , Hsuan-Ling Kao
IPC分类号： H01L218242
CPC分类号： H01L27/112 , H01L27/11253 , H01L27/1126
摘要： A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.
摘要翻译：提供了一种制造具有二极管单元的掩模只读存储器的方法。在位线上形成具有第一导电性的掺杂导电层。然后，在用作蚀刻掩模的掺杂导电层上的层间电介质层上形成具有掩模ROM图案的光致抗蚀剂层，从而在层间电介质层中向掺杂导电层的暴露区域形成开口。进行离子注入以形成具有与掺杂导电层的每个暴露区域中的第一导电性相反的第二导电性的扩散区域，使得在其中形成的掺杂导电层和扩散区域构成用作存储单元的二极管单元。在二极管单元的每个开口中形成接触塞，并且在接触插塞上形成用作字线的导电层。

8. 发明授权

US07723757B2 Vertical nonvolatile memory cell, array, and operation 有权
标题翻译：垂直非易失性存储单元，阵列和操作
公开(公告)号：US07723757B2
公开(公告)日：2010-05-25
申请号：US11774452
申请日：2007-07-06
申请人： Tien Fan Ou , Wen-Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
发明人： Tien Fan Ou , Wen-Jer Tsai , Hsuan Ling Kao , Yi Ying Liao
IPC分类号： H01L29/74
CPC分类号： G11C16/0416 , G11C16/10 , H01L27/1026 , H01L27/115 , H01L27/11568 , H01L29/4234 , H01L29/7923 , H01L29/7926
摘要： A vertical nonvolatile memory cell with a charge storage structure includes a charge control structure with three nodes. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.
摘要翻译：具有电荷存储结构的垂直非易失性存储单元包括具有三个节点的电荷控制结构。示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

9. 发明申请

US20060172490A1 Method of improving flash memory performance 有权
公开(公告)号：US20060172490A1
公开(公告)日：2006-08-03
申请号：US11049230
申请日：2005-02-02
申请人： Pei-Ren Jeng , Hsuan-Ling Kao
发明人： Pei-Ren Jeng , Hsuan-Ling Kao
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/66825
摘要： A method of improving flash memory performance. The method includes: providing a substrate having a gate structure thereon, the gate structure having a gate dielectric layer, a first polysilicon layer, an interploy dielectric layer, and a second polysilicon layer; then, depositing an gate insulating layer to enclose the gate structure, for forming side wall spacers; next, performing a first anneal on the substrate and the enclosed gate structure; then, performing a cell reoxidation on the substrate and the enclosed gate structure by dilute oxidation process using mixed gas comprising oxygen O2 and nitrogen N2. The invention reduces encroachment issues in the interpoly dielectric layer and the tunnel oxide and improves gate coupling ratio (GCR).

10. 发明授权

US07005696B2 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US07005696B2
公开(公告)日：2006-02-28
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

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