专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09310431B2 Diagnosis framework to shorten yield learning cycles of advanced processes 有权
标题翻译：诊断框架来缩短先进过程的产量学习周期
公开(公告)号：US09310431B2
公开(公告)日：2016-04-12
申请号：US13588155
申请日：2012-08-17
申请人： Yen-Ling Liu , Nan-Hsin Tseng , Ji-Jan Chen , Wei-Pin Changchien , Samuel C. Pan
发明人： Yen-Ling Liu , Nan-Hsin Tseng , Ji-Jan Chen , Wei-Pin Changchien , Samuel C. Pan
IPC分类号： G01R31/302 , G01R31/317 , G01R31/3183 , G01R31/02
CPC分类号： G01R31/31704 , G01R31/025 , G01R31/318357
摘要： The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).
摘要翻译：本公开涉及一种诊断框架，用于缩短从高缺陷密度阶段到技术成熟度的技术节点制造过程的产量学习周期。多个待测缺陷（DUT）结构被设计为捕获与缺陷形成相关的潜在制造问题。通过将DUT结构布置在DUT载体单元内而形成测试结构，该DUT载体单元已经通过启发式产量分析进行了屈服强化，使得DUT载体单元的缺陷密度基本上为零。在DUT载体单元中的DUT结构内形成的缺陷相关联的测试模式和各种故障情形的应用的可能结果被模拟并存储在查找表（LUT）中。然后可以参考LUT以确定测试结构内的缺陷的位置，而不需要迭代分析来正确地选择用于物理故障分析（PFA）的缺陷候选。

2. 发明申请

US20140049281A1 Diagnosis Framework to Shorten Yield Learning Cycles of Advanced Processes 有权
标题翻译：诊断框架，缩短先进过程的产量学习周期
公开(公告)号：US20140049281A1
公开(公告)日：2014-02-20
申请号：US13588155
申请日：2012-08-17
申请人： Yen-Ling Liu , Nan-Hsin Tseng , Ji-Jan Chen , Wei-Pin Changchien , Samuel C. Pan
发明人： Yen-Ling Liu , Nan-Hsin Tseng , Ji-Jan Chen , Wei-Pin Changchien , Samuel C. Pan
IPC分类号： G01R31/02 , G06F17/50
CPC分类号： G01R31/31704 , G01R31/025 , G01R31/318357
摘要： The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).
摘要翻译：本公开涉及一种诊断框架，用于缩短从高缺陷密度阶段到技术成熟度的技术节点制造过程的产量学习周期。多个待测缺陷（DUT）结构被设计为捕获与缺陷形成相关的潜在制造问题。通过将DUT结构布置在DUT载体单元内而形成测试结构，该DUT载体单元已经通过启发式产量分析进行了屈服强化，使得DUT载体单元的缺陷密度基本上为零。在DUT载体单元中的DUT结构内形成的缺陷相关联的测试模式和各种故障情形的应用的可能结果被模拟并存储在查找表（LUT）中。然后可以参考LUT以确定测试结构内的缺陷的位置，而不需要迭代分析来正确地选择用于物理故障分析（PFA）的缺陷候选。

3. 发明授权

US06882575B2 Erasing method for non-volatile memory 有权
标题翻译：非易失性存储器的擦除方法
公开(公告)号：US06882575B2
公开(公告)日：2005-04-19
申请号：US10790994
申请日：2004-03-01
申请人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu , Samuel C. Pan
发明人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu , Samuel C. Pan
IPC分类号： G11C16/14 , G11C7/00
CPC分类号： G11C16/14
摘要： An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.
摘要翻译：提供了一种用于非易失性存储器的存储单元的擦除方法。每个存储单元包括栅极，源极，漏极，电子俘获层和衬底。通过向控制栅极施加第一电压，向源施加第二电压，向漏极施加第三电压并向衬底施加第四电压来擦除存储单元内的数据。通过负栅极F-N隧道效应将电子从电子捕获层拉入沟道。

4. 发明授权

US06829175B2 Erasing method for non-volatile memory 有权
标题翻译：非易失性存储器的擦除方法
公开(公告)号：US06829175B2
公开(公告)日：2004-12-07
申请号：US10289866
申请日：2002-11-06
申请人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu , Samuel C. Pan
发明人： Wen-Jer Tsai , Chih-Chieh Yeh , Tao-Cheng Lu , Samuel C. Pan
IPC分类号： G11C700
CPC分类号： G11C16/14
摘要： An erasing method for the memory cells of a non-volatile memory is provided. Each memory cell comprises a gate, a source, a drain, an electron-trapping layer and a substrate. The data within the memory cell is erased by applying a first voltage to the control gate, applying a second voltage to the source, applying a third voltage to the drain and applying a fourth voltage to the substrate. The electrons are pulled from the electron-trapping layer into the channel by negative gate F-N tunneling effect.
摘要翻译：提供了一种用于非易失性存储器的存储单元的擦除方法。每个存储单元包括栅极，源极，漏极，电子俘获层和衬底。通过向控制栅极施加第一电压，向源施加第二电压，向漏极施加第三电压并向衬底施加第四电压来擦除存储单元内的数据。通过负栅极F-N隧道效应将电子从电子捕获层拉入沟道。

5. 发明授权

US06248631B1 Method for forming a v-shaped floating gate 有权
标题翻译：用于形成v形浮动门的方法
公开(公告)号：US06248631B1
公开(公告)日：2001-06-19
申请号：US09415788
申请日：1999-10-08
申请人： Chin-Yi Huang , Yun Chang , Samuel C. Pan
发明人： Chin-Yi Huang , Yun Chang , Samuel C. Pan
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , H01L27/115
摘要： The invention provides a floating gate memory cell, where the floating gate comprises a first lateral end region and a second lateral end region. A middle region is positioned towards a middle of the floating gate with respect to the first lateral end region and the second lateral end region. The thickness of the floating gate decreases continuously from at least one of the first or second lateral end regions to the middle region. This invention also provides for a method of forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon structure between a first alignment structure and a second alignment structure, where the polysilicon structure has a maximum thickness at a first lateral end region adjacent to the first alignment structure and at a second lateral end region adjacent to the second alignment structure, and where the polysilicon structure has a minimum thickness at a middle region positioned between the first lateral end regions and the second lateral end region. The method further includes forming a polysilicon layer over the polysilicon structure such that the polysilicon layer adopts a contour of the polysilicon structure.
摘要翻译：本发明提供一种浮动栅极存储单元，其中浮动栅极包括第一侧向端部区域和第二侧向端部区域。中间区域相对于第一横向端部区域和第二横向端部区域朝向浮动栅极的中间定位。浮动栅极的厚度从第一或第二横向端部区域中的至少一个到中间区域连续地减小。本发明还提供了一种形成用于浮动栅极存储单元的轮廓浮动栅极的方法。该方法包括在第一对准结构和第二对准结构之间形成多晶硅结构，其中多晶硅结构在与第一对准结构相邻的第一横向端部区域处具有最大厚度，并且在邻近第二对准结构的第二横向端部区域结构，并且其中多晶硅结构在位于第一侧端部区域和第二侧向端部区域之间的中间区域处具有最小厚度。该方法还包括在多晶硅结构上形成多晶硅层，使得多晶硅层采用多晶硅结构的轮廓。

6. 发明授权

US06177317B1 Method of making nonvolatile memory devices having reduced resistance diffusion regions 有权
标题翻译：制造具有减小的电阻扩散区域的非易失性存储器件的方法
公开(公告)号：US06177317B1
公开(公告)日：2001-01-23
申请号：US09291915
申请日：1999-04-14
申请人： Chin-Yi Huang , Huei Huarng Chen , Yun Chang , Samuel C. Pan
发明人： Chin-Yi Huang , Huei Huarng Chen , Yun Chang , Samuel C. Pan
IPC分类号： H01L218247
CPC分类号： H01L27/11521
摘要： A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist masking process is performed on the multilayer structure to define gates of the nonvolatile memory device. A spacer layer is then deposited and etched back to form sidewall spacers adjacent the gates. The width of the sidewall spacers is used to define the width of the source and drain regions, and the width of trenches between the gates. Trenches are formed using a high selectivity etch which etches through the substrate faster than the sidewall spacers and the etch stop layer. A conductive layer is formed over the area of the device and etched to form the reduced resistance diffusion regions and the desired trench configuration. The trenches are then filled with an insulating material.
摘要翻译：描述了一种用于制造具有减小的电阻扩散区域的非易失性存储器件的方法。该方法的一个实施例包括在包括隧道氧化物层，多晶硅层和蚀刻停止层的衬底上形成多层结构。在多层结构上执行光致抗蚀剂掩模处理以限定非易失性存储器件的栅极。然后沉积间隔层并回蚀刻以形成邻近栅极的侧壁间隔物。侧壁间隔物的宽度用于限定源极和漏极区域的宽度以及栅极之间的沟槽的宽度。使用高选择性蚀刻形成沟槽，其蚀刻通过衬底比侧壁间隔物和蚀刻停止层更快。在器件的区域上形成导电层并进行蚀刻以形成减小的电阻扩散区域和所需的沟槽结构。然后用绝缘材料填充沟槽。

7. 发明授权

US3989466A Liquid-liquid extraction apparatus including fibrous strand packing 失效
标题翻译：液 - 液萃取装置包括纤维束包装
公开(公告)号：US3989466A
公开(公告)日：1976-11-02
申请号：US388045
申请日：1973-08-13
申请人： Samuel C. Pan
发明人： Samuel C. Pan
IPC分类号： B01D11/04 , B01D11/00 , B01D15/02 , B01D59/22
CPC分类号： B01D11/043
摘要： Apparatus is provided for use in carrying out liquid-liquid extraction techniques, which apparatus includes an extraction column containing a unique solvent sorbing packing material, namely a plurality or bundle of elongated fibrous strands having first and second end portions, the strands being capable of sorbing a desired solvent; the apparatus also includes a separation zone in communication with the second end of the plurality of fibrous strands, means for feeding a first or heavy solvent phase through the bundle of fibrous strands so as to be sorbed by said strands, and subsequently into the separation zone, means for feeding a second or light solvent phase into the separation zone and thence through the annular spaces of the column, around the fibrous strands contained therein, means for recovering the light solvent phase from the first end of said bundle and means for recovering said heavy solvent phase from said separation zone. Apparatus for separating two components by extraction techniques is also provided wherein the fibrous strand packing is utilized. A process is also provided for carrying out a continuous liquid-liquid countercurrent extraction employing two continuous phases. The process is carried out employing apparatus as described above.
摘要翻译：提供用于进行液 - 液萃取技术的装置，该装置包括一个提取塔，该提取塔含有独特的溶剂吸附包装材料，即具有第一和第二端部分的多根或一束细长的纤维束，该股线能够吸附所需溶剂; 该装置还包括与多个纤维束的第二端连通的分离区，用于将第一或重溶剂相通过纤维束束进行供给以被所述丝束吸附的装置，随后进入分离区用于将第二或轻质溶剂相进料到所述分离区中并且从而通过所述塔的环形空间围绕其中包含的纤维束的装置，用于从所述束的第一端回收轻溶剂相的装置和用于回收所述来自所述分离区的重溶剂相。还提供了通过提取技术分离两种组分的装置，其中使用纤维束包装。还提供了一种用于进行采用两个连续相的连续液 - 液逆流萃取的方法。使用如上所述的装置进行处理。

8. 发明授权

US06413818B1 Method for forming a contoured floating gate cell 有权
标题翻译：形成轮廓浮动栅极的方法
公开(公告)号：US06413818B1
公开(公告)日：2002-07-02
申请号：US09415936
申请日：1999-10-08
申请人： Chin-Yi Huang , Chih-Jen Huang , Yun Chang , James Hsu , Samuel C. Pan
发明人： Chin-Yi Huang , Chih-Jen Huang , Yun Chang , James Hsu , Samuel C. Pan
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42324
摘要： A floating gate having a first and second end region, each of which are positioned adjacent to a corresponding lateral end of the floating gate. A middle region is positioned laterally towards a middle of the floating gate relative to the first and second end regions. The first end region, the middle region and the second end region are formed of a same material during a single fabrication step, and the middle region formed has a thickness which is less than a thickness of the first or second end regions. This invention further includes a method for forming a contoured floating gate for use in a floating gate memory cell. The method includes forming a polysilicon layer over first and second spaced apart oxide structures and a floating gate region between the first and second oxide structures such that the polysilicon layer formed in the floating gate region has a first end region adjacent the first oxide structure, a second end region adjacent the second oxide structure, and a middle region positioned laterally between the first and second end regions. The method further includes removing a portion of the polysilicon layer in the floating gate region such that the vertical thickness of the first and second end regions remain greater than the vertical thickness of the middle region.
摘要翻译：一种具有第一和第二端区域的浮动栅极，每个都与浮置栅极的相应横向端相邻。中间区域相对于第一和第二端部区域侧向朝向浮动门的中间定位。在单个制造步骤期间，第一端区域，中间区域和第二端部区域由相同的材料形成，并且形成的中间区域的厚度小于第一或第二端部区域的厚度。本发明还包括一种用于形成在浮动栅极存储单元中使用的轮廓浮动栅极的方法。该方法包括在第一和第二间隔开的氧化物结构之上形成多晶硅层和在第一和第二氧化物结构之间的浮栅区域，使得形成在浮动栅极区域中的多晶硅层具有与第一氧化物结构相邻的第一端区域，与第二氧化物结构相邻的第二端区域和位于第一和第二端部区域之间横向定位的中间区域。该方法还包括去除浮动栅极区域中的多晶硅层的一部分，使得第一和第二端部区域的垂直厚度保持大于中间区域的垂直厚度。

9. 发明授权

US3616227A Synthesis of steroids 失效
公开(公告)号：US3616227A
公开(公告)日：1971-10-26
申请号：US3616227D
申请日：1968-09-16
申请人： SAMUEL C PAN , LEONARD J LERNER
发明人： PAN SAMUEL C , LERNER LEONARD J
IPC分类号： C07J17/00 , C07J75/00 , C07C167/00
CPC分类号： C07J17/00 , C07J75/00
摘要： This invention relates to Alpha -glucosides of steroids containing hydroxy groups in both the 16 Alpha - and 17-positions and the method for preparing them by reacting with a polysaccharide or an oligosaccharide, such as maltose, in the presence of a source of the enzyme: amylase or transglucosylase. The Alpha -glucosides are new compounds that possess estrogenic activity. They may be used, therefore, as antifertility agents.

10. 发明授权

US06787056B2 Planarization method using anisotropic wet etching 有权
标题翻译：使用各向异性湿蚀刻的平面化方法
公开(公告)号：US06787056B2
公开(公告)日：2004-09-07
申请号：US10067260
申请日：2002-02-07
申请人： Wen-Bin Tsai , Ching-Yu Chang , Chun-Pei Wu , Huei-Huang Chen , Samuel C. Pan
发明人： Wen-Bin Tsai , Ching-Yu Chang , Chun-Pei Wu , Huei-Huang Chen , Samuel C. Pan
IPC分类号： B44C122
CPC分类号： H01L21/31055 , H01L21/31111
摘要： A planarization method using anisotropic etching can be applied to planarize an insulating layer with an uneven surface on a substrate. H2SO4, H3PO4, HF and H2O are mixed to form an etching solution. The substrate is placed into the etching solution to make the etching solution pass the surface of the insulating layer at a flow rate to etch the insulating layer. After a period of etching time, the insulating layer with a more planar surface can be obtained.
摘要翻译：可以应用使用各向异性蚀刻的平面化方法来平坦化具有基板上的不平坦表面的绝缘层。将H 2 SO 4，H 3 PO 4，HF和H 2 O混合以形成蚀刻溶液。将衬底放置在蚀刻溶液中以使蚀刻溶液以流速通过绝缘层的表面以蚀刻绝缘层。经过一段时间的蚀刻时间后，可获得具有更平坦表面的绝缘层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式