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1. 发明申请

US20050040467A1 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US20050040467A1
公开(公告)日：2005-02-24
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/8247 , H01L27/108 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

2. 发明申请

US20060154441A1 Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate 有权
标题翻译：用于在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法
公开(公告)号：US20060154441A1
公开(公告)日：2006-07-13
申请号：US11032045
申请日：2005-01-11
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.
摘要翻译：提供一种在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法。图案化的第一介电层形成在半导体衬底上用作第一硬掩模。进行热氧化处理以在半导体衬底的暴露的部分上形成场氧化物。然后去除图案化的第一介电层。在场氧化物和半导体衬底上形成用作第二硬掩模的第二图案化电介质层。执行各向同性蚀刻工艺以蚀刻场氧化物和半导体衬底的暴露部分。图案化的第二介电层和下面的场氧化物被去除以在半导体衬底的表面上形成多个沟槽。沿着半导体衬底中的沟槽的周围形成掩埋扩散层。

3. 发明授权

US07244661B2 Method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate 有权
标题翻译：用于在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法
公开(公告)号：US07244661B2
公开(公告)日：2007-07-17
申请号：US11032045
申请日：2005-01-11
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L21/76
CPC分类号： H01L27/115 , H01L27/11521
摘要： A method for forming a buried diffusion layer with reducing topography in a surface of a semiconductor substrate is provided. A patterned first dielectric layer is formed on a semiconductor substrate for being used as a first hard mask. A thermal oxidation process is performed to form field oxides on the exposed potions of the semiconductor substrate. The patterned first dielectric layer is then removed. A second patterned dielectric layer is formed on the field oxides and the semiconductor substrate for being used as a second hard mask. An isotropic etching process is performed to etch the exposed portions of the field oxides and the semiconductor substrate. The patterned second dielectric layer and the underlying field oxides are removed to form a plurality of trenches on the surface of the semiconductor substrate. A buried diffusion layer is formed along surroundings of the trenches in the semiconductor substrate.
摘要翻译：提供一种在半导体衬底的表面中形成具有减小的形貌的掩埋扩散层的方法。图案化的第一介电层形成在半导体衬底上用作第一硬掩模。进行热氧化处理以在半导体衬底的暴露的部分上形成场氧化物。然后去除图案化的第一介电层。在场氧化物和半导体衬底上形成用作第二硬掩模的第二图案化电介质层。执行各向同性蚀刻工艺以蚀刻场氧化物和半导体衬底的暴露部分。图案化的第二介电层和下面的场氧化物被去除以在半导体衬底的表面上形成多个沟槽。沿着半导体衬底中的沟槽的周围形成掩埋扩散层。

4. 发明授权

US07005696B2 Structure of nonvolatile memory array 有权
标题翻译：非易失性存储器阵列的结构
公开(公告)号：US07005696B2
公开(公告)日：2006-02-28
申请号：US10644902
申请日：2003-08-21
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hsuan-Ling Kao
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A structure of a nonvolatile memory array with low source line sheet resistance is disclosed in this present invention. The key aspect of this present invention is employing a buried conductive region as the source line of a nonvolatile memory array. The topology of the above-mentioned buried conductive region is different from the source line in the prior art. Therefore, this invention can provide a nonvolatile memory array for reducing the source line sheet resistance and achieving the reliability and the operating performance of the nonvolatile memory array.
摘要翻译：在本发明中公开了具有低源极线电阻的非易失性存储器阵列的结构。本发明的关键方面是采用埋入导电区域作为非易失性存储器阵列的源极线。上述掩埋导电区域的拓扑与现有技术中的源极线不同。因此，本发明可以提供一种用于减少源极线电阻并实现非易失性存储器阵列的可靠性和操作性能的非易失性存储器阵列。

5. 发明授权

US08097912B2 Systems and methods for self convergence during erase of a non-volatile memory device 有权
标题翻译：用于在非易失性存储器件擦除期间自会聚的系统和方法
公开(公告)号：US08097912B2
公开(公告)日：2012-01-17
申请号：US11762677
申请日：2007-06-13
申请人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
发明人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
IPC分类号： H01L21/8247 , H01L29/788
CPC分类号： H01L27/115 , G11C16/3404 , G11C16/3409 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.
摘要翻译：非易失性存储器件通过控制栅极结构中的电介质层以及整个栅极结构的物理方面，例如厚度，宽度，面积等来在正常擦除周期期间实现自会聚。还可以在正常擦除周期期间通过在擦除周期期间斜坡施加到控制栅极的擦除电压来辅助自会聚。

6. 发明申请

US20080308857A1 Systems and Methods for Self Convergence During Erase of a Non-Volatile Memory Device 有权
标题翻译：擦除非易失性存储器件期间自收敛的系统和方法
公开(公告)号：US20080308857A1
公开(公告)日：2008-12-18
申请号：US11762677
申请日：2007-06-13
申请人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
发明人： Cheng-Ming Yih , Chu-Ching Wu , Huei-Huarng Chen
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , G11C16/3404 , G11C16/3409 , H01L21/28273 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device implements self-convergence during the normal erase cycle through control of physical aspects, such as thickness, width, area, etc., of the dielectric layers in the gate structure as well as of the overall gate structure. Self-convergence can also be aided during the normal erase cycle by ramping the erase voltage applied to the control gate during the erase cycle.
摘要翻译：非易失性存储器件通过控制栅极结构中的电介质层以及整个栅极结构的物理方面，例如厚度，宽度，面积等来在正常擦除周期期间实现自会聚。还可以在正常擦除周期期间通过在擦除周期期间斜坡施加到控制栅极的擦除电压来辅助自会聚。

7. 发明申请

US20050006795A1 Corner free structure of nonvolatile memory 审中-公开
标题翻译：非易失性存储器的无角结构
公开(公告)号：US20050006795A1
公开(公告)日：2005-01-13
申请号：US10614892
申请日：2003-07-09
申请人： Cheng-Ming Yih , Huei-Huarng Chen , Hong-Chi Chen
发明人： Cheng-Ming Yih , Huei-Huarng Chen , Hong-Chi Chen
IPC分类号： H01L21/336 , H01L27/108 , H01L29/423 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/42324 , H01L29/7883
摘要： A corner free structure of a nonvolatile memory is disclosed in this present invention. The key aspect of this present invention is employing a corner free structure for isolating a trench isolation device and a nonvolatile memory, and thus the reliability of the above-mentioned nonvolatile memory is improved. Furthermore, based on the definition of coupling ratio, as a result of the above-cited corner free structure, the effective channel area of the nonvolatile memory is modified, and thus the nonvolatile memory according to this present invention can achieve higher efficiency than the nonvolatile memory in the prior art. Therefore, this invention can not only improve the reliability of a nonvolatile memory, but also advance the efficiency of the nonvolatile memory.
摘要翻译：在本发明中公开了非易失性存储器的无角结构。本发明的关键方面是采用无角结构来隔离沟槽隔离装置和非易失性存储器，从而提高了上述非易失性存储器的可靠性。此外，基于耦合比的定义，作为上述无角结构的结果，非易失性存储器的有效沟道面积被修改，因此根据本发明的非易失性存储器可以实现比非易失性存储器更高的效率现有技术中的记忆。因此，本发明不仅可以提高非易失性存储器的可靠性，而且可以提高非易失性存储器的效率。

8. 发明授权

US08043908B2 Method of fabricating memory 有权
标题翻译：制造记忆的方法
公开(公告)号：US08043908B2
公开(公告)日：2011-10-25
申请号：US12851790
申请日：2010-08-06
申请人： Cheng-Ming Yih
发明人： Cheng-Ming Yih
IPC分类号： H01L21/8238
CPC分类号： H01L29/7881 , H01L21/28247 , H01L21/28273 , H01L29/42324
摘要： A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.
摘要翻译：提供一种制造半导体器件的方法。首先，在基板上形成层叠结构。叠层结构依次包括介质层和导电栅极。执行离子注入工艺以在层叠结构的相对侧上的衬底中形成掺杂区域。此后，在层叠结构的侧壁上形成源极间隔物。执行热处理以激活掺杂区域，从而在层叠结构的侧壁的衬底内形成源，该层的结构具有源极侧隔离物和衬底中位于堆叠结构另一侧的漏极。

9. 发明申请

US20070042544A1 Low-k spacer structure for flash memory 有权
标题翻译：用于闪存的Low-k间隔结构
公开(公告)号：US20070042544A1
公开(公告)日：2007-02-22
申请号：US11204537
申请日：2005-08-16
申请人： Chu-Ching Wu , Cheng-Ming Yih
发明人： Chu-Ching Wu , Cheng-Ming Yih
IPC分类号： H01L21/336
CPC分类号： H01L29/6656 , H01L21/28273 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： A flash memory cell includes a silicon substrate having a main surface, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. The memory cell includes a first dielectric layer formed on the main surface, a floating gate disposed above the first dielectric layer, an inter-gate dielectric layer disposed above the floating gate, a control gate disposed above the inter-gate dielectric layer, a second dielectric layer and a low-k dielectric spacer layer disposed on the second dielectric layer. The first dielectric layer covers a portion of the main surface between the source and the drain. The second dielectric layer surrounds outer portions of the first dielectric layer, the control gate, the inter-gate dielectric layer and the floating gate.
摘要翻译：闪存单元包括具有主表面的硅衬底，位于主表面附近的硅衬底的一部分中的源极区域和位于主表面附近的硅衬底的一部分中的漏极区域。漏极区域与源极区域间隔开。所述存储单元包括形成在所述主表面上的第一介电层，设置在所述第一介电层上方的浮置栅极，设置在所述浮置栅极上方的栅极间电介质层，设置在所述栅极间电介质层上方的控制栅极，电介质层和设置在第二电介质层上的低k电介质间隔层。第一电介质层覆盖源极和漏极之间的主表面的一部分。第二电介质层围绕第一电介质层，控制栅极，栅极间电介质层和浮置栅极的外部部分。

10. 发明申请

US20120273842A1 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US20120273842A1
公开(公告)日：2012-11-01
申请号：US13549272
申请日：2012-07-13
申请人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
发明人： Chun-Yuan Lo , Cheng-Ming Yih , Wen-Pin Lu
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11519 , G11C5/005 , G11C5/025 , G11C5/063 , G11C8/14 , H01L27/11565
摘要： A memory array including a plurality of memory cells, a plurality of word lines, a dummy word line, and a plug is provided. Each word line is coupled to corresponding memory cells. A dummy word line is directly adjacent to an outmost word line of the plurality of word lines. The plug is located between the dummy word line and the outmost word line.
摘要翻译：提供了包括多个存储单元，多个字线，虚拟字线和插头的存储器阵列。每个字线耦合到相应的存储单元。虚拟字线与多个字线的最外侧字线直接相邻。插头位于虚拟字线和最外面的字线之间。

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