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1. 发明授权

US08836116B2 Wafer level packaging of micro-electro-mechanical systems (MEMS) and complementary metal-oxide-semiconductor (CMOS) substrates 有权
标题翻译：微电子机械系统（MEMS）和互补金属氧化物半导体（CMOS）基板的晶片级封装
公开(公告)号：US08836116B2
公开(公告)日：2014-09-16
申请号：US12944118
申请日：2010-11-11
申请人： Hsueh-An Yang
发明人： Hsueh-An Yang
IPC分类号： H01L29/72 , B81C1/00 , H01L23/48 , H01L23/31 , H01L21/768
CPC分类号： H01L23/481 , B81B7/008 , B81C1/0023 , B81C1/00238 , B81C1/00571 , B81C2203/0771 , H01L21/76 , H01L21/76885 , H01L21/76898 , H01L23/3171 , H01L23/53238 , H01L2224/0401 , H01L2224/05 , H01L2224/05569 , H01L2224/13 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/1461 , H01L2924/00 , H01L2224/05552
摘要： The embodiments of methods and structures for forming through silicon vias a CMOS substrate bonded to a MEMS substrate and a capping substrate provide mechanisms for integrating CMOS and MEMS devices that use less real-estate and are more reliable. The through silicon vias electrically connect to metal-1 level of the CMOS devices. Copper metal may be plated on a barrier/Cu-seed layer to partially fill the through silicon vias, which saves time and cost. The formation method may involve using dual dielectric layers on the substrate surface as etching mask to eliminate a photolithographical process during the removal of oxide layer at the bottoms of through silicon vias. In some embodiments, the through silicon vias land on polysilicon gate structures to prevent notch formation during etching of the vias.
摘要翻译：用于形成硅通孔的方法和结构的实施例与粘合到MEMS衬底和封盖衬底的CMOS衬底提供用于集成使用较少不动产且更可靠的CMOS和MEMS器件的机制。通孔硅通孔电连接到CMOS器件的金属1级。铜金属可以镀在阻挡层/ Cu籽晶层上以部分地填充通过硅通孔，这节省了时间和成本。形成方法可以包括在衬底表面上使用双电介质层作为蚀刻掩模，以在通过硅通孔的底部去除氧化物层期间消除光刻工艺。在一些实施例中，穿通硅通孔着陆在多晶硅栅极结构上，以防止在蚀刻过孔期间形成凹陷。

2. 发明授权

US08318511B2 Integration manufacturing process for MEMS device 失效
公开(公告)号：US08318511B2
公开(公告)日：2012-11-27
申请号：US13343643
申请日：2012-01-04
申请人： Mingching Wu , Hsueh-An Yang , Hung-Yi Lin , Weileun Fang
发明人： Mingching Wu , Hsueh-An Yang , Hung-Yi Lin , Weileun Fang
IPC分类号： H01L31/26
CPC分类号： B81C1/00301 , B81B2201/042 , B81B2207/097
摘要： A method for manufacturing an MEMS device is provided. The method includes steps of a) providing a first substrate having a concavity located thereon, b) providing a second substrate having a connecting area and an actuating area respectively located thereon, c) forming plural microstructures in the actuating area, d) mounting a conducting element in the connecting area and the actuating area, e) forming an insulating layer on the conducting element and f) connecting the first substrate to the connecting area to form the MEMS device. The concavity contains the plural microstructures.

3. 发明申请

US20090215228A1 WAFER LEVER FIXTURE AND METHOD FOR PACKAGING MICRO-ELECTRO-MECHANICAL-SYSTEM DEVICES 有权
标题翻译：用于包装微电子机械系统装置的滤波器装置和方法
公开(公告)号：US20090215228A1
公开(公告)日：2009-08-27
申请号：US12057949
申请日：2008-03-28
申请人： Hsueh An YANG
发明人： Hsueh An YANG
IPC分类号： H01L21/98 , H05K1/16 , G03F7/20
CPC分类号： B81C1/00269 , B81C2203/0127
摘要： A fixture for packaging MEMS devices includes a base, a first material layer, an insulating layer and a second material layer. The base defines units, each including a notch. The first material layer is disposed on the base and the notches. The insulating layer is disposed on a part of the first material layer and exposes the other part of the first material layer located on the notches. The second material layer is disposed on the other part of the first material layer and formed with caps, whereby the caps are physically connected to the MEMS devices, and the MEMS devices are corresponding to the units of the base, wherein there is a first connecting force between the first and second material layers, there is a second connecting force between the caps and the MEMS devices, and the second connecting force is greater than the first connecting force.
摘要翻译：用于封装MEMS器件的夹具包括基底，第一材料层，绝缘层和第二材料层。基座定义单元，每个单元包括一个凹口。第一材料层设置在基部和凹口上。绝缘层设置在第一材料层的一部分上并暴露位于凹口上的第一材料层的另一部分。第二材料层设置在第一材料层的另一部分上并形成有盖，由此盖物理连接到MEMS器件，并且MEMS器件对应于基座的单元，其中存在第一连接在第一和第二材料层之间的力，帽和MEMS器件之间存在第二连接力，并且第二连接力大于第一连接力。

4. 发明申请

US20090046436A1 MICRO-ELECTRO-MECHANICAL-SYSTEM PACKAGE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：微电子机械系统包装及其制造方法
公开(公告)号：US20090046436A1
公开(公告)日：2009-02-19
申请号：US12126043
申请日：2008-05-23
申请人： Hsueh An YANG , Meng Jen WANG , Wei Chung WANG , Ming Chiang LEE , Wei Pin HUANG , Feng Chen CHENG
发明人： Hsueh An YANG , Meng Jen WANG , Wei Chung WANG , Ming Chiang LEE , Wei Pin HUANG , Feng Chen CHENG
IPC分类号： H05K1/00 , H05K3/10
CPC分类号： B81C1/0023 , B81B2201/0257 , H01L2224/48091 , H01L2224/48227 , H01L2924/1461 , H01L2924/3025 , Y10T29/49162 , H01L2924/00014 , H01L2924/00
摘要： A MEMS package includes a first board, a second board and a laminate material. The first board includes a lower metallic trace, a metallic diaphragm and a through opening. The lower metallic trace is located on the lower surface of the first board, and the metallic diaphragm is disposed on the lower metallic trace. The second board includes an upper metallic trace and a metallic electrode. The upper metallic trace is located on the upper surface of the second board, the metallic electrode is disposed on the upper metallic trace, and the metallic electrode is corresponding to the metallic diaphragm. The laminate material is disposed between the lower and upper metallic traces, and includes a hollow portion for accommodating the metallic electrode and metallic diaphragm, wherein a sensing unit is formed by the metallic electrode, the hollow portion and the metallic diaphragm, and is corresponding to the through opening.
摘要翻译： MEMS封装包括第一板，第二板和层压材料。第一板包括下金属痕迹，金属隔膜和通孔。下部金属轨迹位于第一板的下表面上，并且金属隔膜设置在下部金属轨迹上。第二板包括上金属痕迹和金属电极。上金属轨迹位于第二板的上表面上，金属电极设置在上金属轨迹上，金属电极对应于金属隔膜。层压材料设置在下金属轨迹和上金属迹线之间，并且包括用于容纳金属电极和金属隔膜的中空部分，其中感测单元由金属电极，中空部分和金属隔膜形成，并且对应于通过开口。

5. 发明申请

US20080197951A1 DRIVING METHOD FOR MAGNETIC ELEMENT 审中-公开
标题翻译：磁性元件的驱动方法
公开(公告)号：US20080197951A1
公开(公告)日：2008-08-21
申请号：US11842304
申请日：2007-08-21
申请人： Hsueh-An YANG , Weileun FANG , Tsung-Lin TANG
发明人： Hsueh-An YANG , Weileun FANG , Tsung-Lin TANG
IPC分类号： H01F7/02
CPC分类号： H01F7/14 , G02B26/085 , H01F7/0289 , H01F7/081 , H01F2007/068
摘要： A method for driving a magnetic element is provided. The method includes steps of: a) providing a first magnetic field, b) providing a second magnetic field interacting with the first magnetic field to generate a magnetostatic field, c) putting the magnetic element into the magnetostatic field, and d) generating a magnetic torque by modulating the first magnetic field and the second magnetic field so as to drive the magnetic element.
摘要翻译：提供了一种用于驱动磁性元件的方法。该方法包括以下步骤：a）提供第一磁场，b）提供与第一磁场相互作用的第二磁场以产生静磁场，c）将磁性元件放入静磁场，以及d）产生磁通过调制第一磁场和第二磁场来驱动磁性元件的转矩。

6. 发明申请

US20070205499A1 Microelectromechanical microphone packaging system 有权
标题翻译：微机电麦克风包装系统
公开(公告)号：US20070205499A1
公开(公告)日：2007-09-06
申请号：US11645598
申请日：2006-12-27
申请人： Wei-Chung Wang , Sung-Mao Wu , Hsueh-An Yang , Kuo-Pin Yang , Chian-Chi Lin
发明人： Wei-Chung Wang , Sung-Mao Wu , Hsueh-An Yang , Kuo-Pin Yang , Chian-Chi Lin
IPC分类号： H01L23/12
CPC分类号： B81B7/0064 , B81B2201/0257 , H01L23/3121 , H01L24/48 , H01L2224/48091 , H01L2224/48137 , H01L2224/73265 , H01L2224/8592 , H01L2924/00014 , H01L2924/16151 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H04R1/02 , H04R1/04 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.
摘要翻译：本发明涉及一种微机电麦克风包装系统。微电机麦克风包装系统包括基片，芯片，微电机麦克风，导电胶，非导电胶和盖。衬底具有第一表面。芯片安装在基板的第一表面上。微机电麦克风安装在基板的第一表面上，并与芯片电连接。芯片由非导电胶水封闭。导电胶被导电胶包围。盖安装在基板的第一表面上以形成容纳空间，并具有声孔。微机电麦克风包装系统利用封装芯片和非导电胶的导电胶来屏蔽外部噪声的干扰并获得屏蔽效果。此外，盖子不需要由金属材料制成。

7. 发明授权

US08810027B2 Bond ring for a first and second substrate 有权
标题翻译：用于第一和第二衬底的结合环
公开(公告)号：US08810027B2
公开(公告)日：2014-08-19
申请号：US12891062
申请日：2010-09-27
申请人： Chun-Wen Cheng , Hsueh-An Yang
发明人： Chun-Wen Cheng , Hsueh-An Yang
IPC分类号： H01L23/34 , H01L21/30 , H01L21/46
CPC分类号： B81C1/00269 , B81C1/0038 , B81C2203/0118 , B81C2203/019 , H01L23/02 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a device having a plurality of bonded substrates. The substrates are bonded by a first bond ring and a second bond ring. In an embodiment, the first bond ring is a eutectic bond and the second bond ring is at least one of an organic material and a eutectic bond. The second bond ring encircles the first bond ring. The first bond ring provides a hermetic region of the device. In a further embodiment, a plurality of wafers are bonded which include a third bond ring disposed at the periphery of the wafers.
摘要翻译：本公开提供了一种具有多个键合衬底的器件。基板通过第一键环和第二键环键合。在一个实施方案中，第一键环是共晶键，第二键环是有机材料和共晶键中的至少一种。第二个键环围绕第一个结合环。第一粘结环提供该装置的密封区域。在另一实施例中，多个晶片被结合，其包括设置在晶片周边的第三接合环。

8. 发明授权

US08263493B2 Silicon chip having through via and method for making the same 有权
标题翻译：具有通孔的硅芯片及其制造方法
公开(公告)号：US08263493B2
公开(公告)日：2012-09-11
申请号：US12647856
申请日：2009-12-28
申请人： Hsueh-An Yang , Pei-Chun Chen , Chien-Hua Chen
发明人： Hsueh-An Yang , Pei-Chun Chen , Chien-Hua Chen
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/76898
摘要： The present invention relates to a silicon chip having a through via and a method for making the same. The silicon chip includes a silicon substrate, a passivation layer, at least one electrical device and at least one through via. The passivation layer is disposed on a first surface of the silicon substrate. The electrical device is disposed in the silicon substrate, and exposed to a second surface of the silicon substrate. The through via includes a barrier layer and a conductor, and penetrates the silicon substrate and the passivation layer. A first end of the through via is exposed to the surface of the passivation layer, and a second end of the through via connects the electrical device. When a redistribution layer is formed on the surface of the passivation layer, the redistribution layer will not contact the silicon substrate, thus avoiding a short circuit. Therefore, a lower resolution process can be used, which results in low manufacturing cost and simple manufacturing process.
摘要翻译：本发明涉及具有贯通孔的硅芯片及其制造方法。硅芯片包括硅衬底，钝化层，至少一个电器件和至少一个通孔。钝化层设置在硅衬底的第一表面上。电气设备设置在硅衬底中，并暴露于硅衬底的第二表面。通孔包括阻挡层和导体，并且穿透硅衬底和钝化层。通孔的第一端暴露于钝化层的表面，通孔的第二端连接电气装置。当在钝化层的表面上形成再分布层时，再分布层将不会接触硅衬底，从而避免短路。因此，可以使用较低分辨率的工艺，这导致制造成本低和制造工艺简单。

9. 发明授权

US07863181B2 Method for manufacturing a device having a high aspect ratio via 有权
标题翻译：制造具有高纵横比的装置的方法
公开(公告)号：US07863181B2
公开(公告)日：2011-01-04
申请号：US12170138
申请日：2008-07-09
申请人： Hsueh An Yang , Po Jen Cheng
发明人： Hsueh An Yang , Po Jen Cheng
IPC分类号： H01L21/4763
CPC分类号： H01L21/0272 , H01L21/31144 , H01L21/32115 , H01L24/11 , H01L2224/05001 , H01L2224/05023 , H01L2224/05026 , H01L2224/051 , H01L2224/056 , H01L2924/14 , H01L2924/19041 , H01L2924/00014
摘要： Method for manufacturing a device having a conductive via includes the following steps. A dielectric material layer including a through hole is formed on a substrate. A seed metallic layer is formed on the dielectric material layer and in the through hole. A metallic layer is formed on the seed metallic layer, and is filled in the through hole. The metallic layer located over the seed metallic layer and outside the through hole is etched by a spin etching process, whereby the metallic layer located in the through hole is formed to a lower portion. An upper portion is formed on the lower portion, and a metallic trace is formed on the seed metallic layer, wherein the upper and lower portions is formed to a conductive via, and the conductive via and the metallic trace expose a part of the seed metallic layer. The exposed seed metallic layer is etched.
摘要翻译：具有导电通孔的装置的制造方法包括以下步骤。在基板上形成包括通孔的电介质材料层。在电介质材料层和通孔中形成种子金属层。在种子金属层上形成金属层，并填充在通孔中。通过旋转蚀刻工艺蚀刻位于种子金属层上方的金属层和通孔外部，由此将位于通孔中的金属层形成为下部。在下部形成上部，在种子金属层上形成金属线，其中上部和下部形成为导电通孔，并且导电通孔和金属迹线暴露出种子金属的一部分层。暴露的种子金属层被蚀刻。

10. 发明授权

US07501342B2 Device having high aspect-ratio via structure in low-dielectric material and method for manufacturing the same 有权
标题翻译：在低介电常数材料中具有高纵横比通孔结构的器件及其制造方法
公开(公告)号：US07501342B2
公开(公告)日：2009-03-10
申请号：US12050601
申请日：2008-03-18
申请人： Wei Chung Wang , Po Jen Cheng , Hsueh An Yang , Pei Chun Chen
发明人： Wei Chung Wang , Po Jen Cheng , Hsueh An Yang , Pei Chun Chen
IPC分类号： H01L21/44
CPC分类号： H01L23/5226 , H01L21/02118 , H01L21/312 , H01L23/525 , H01L24/03 , H01L24/05 , H01L2225/06572 , H01L2924/01014 , H01L2924/01019 , H01L2924/01078 , H01L2924/14 , H01L2924/19041
摘要： A method for manufacturing a device having a via structure includes the following steps. A seed metallic layer is formed on a substrate. A patterned metallic-trace layer is formed on the seed metallic layer. A positive-type photoresist layer is formed on the patterned metallic-trace layer and seed metallic layer. The photoresist layer is patterned for defining a through hole which exposes a part of the patterned metallic-trace layer, wherein the through hole has a high aspect ratio. A metallic material is electroplated in the through hole so as to form a metallic pillar. The photoresist layer is removed. A part of the seed metallic layer is etched, whereby traces of the patterned metallic-trace layer are electrically isolated from each other. A dielectric material layer is formed on the substrate for sealing the patterned metallic-trace layer and a part of the metallic pillar and exposing a top surface of the metallic pillar.
摘要翻译：用于制造具有通孔结构的器件的方法包括以下步骤。种子金属层形成在基片上。在种子金属层上形成图案化的金属痕迹层。在图案化的金属痕迹层和种子金属层上形成正型光致抗蚀剂层。图案化光致抗蚀剂层以限定暴露图案化的金属 - 迹线层的一部分的通孔，其中通孔具有高纵横比。在通孔中电镀金属材料，形成金属柱。去除光致抗蚀剂层。蚀刻种子金属层的一部分，由此图案化的金属迹线层的迹线彼此电隔离。在基板上形成电介质材料层，用于密封图案化的金属迹线层和金属柱的一部分并暴露金属柱的顶表面。

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