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1. 发明授权

US07869312B1 Calibration based DC coupled analog front end for optical storage system 有权
标题翻译：基于校准的直流耦合模拟前端用于光存储系统
公开(公告)号：US07869312B1
公开(公告)日：2011-01-11
申请号：US11755463
申请日：2007-05-30
申请人： Yingxuan Li , Fu-Tai An , Yonghua Song
发明人： Yingxuan Li , Fu-Tai An , Yonghua Song
IPC分类号： G11B7/00
CPC分类号： G11B7/0945
摘要： A driver circuit for use with a variety of OPU circuits has both a single-ended input and a differential input. The single-ended input is coupled to a single-ended signal path having a variable gain stage and a variable level shifter. The differential input is coupled to a differential signal path having a variable gain stage and a variable level shifter. The single-ended signal path and the differential signal path may be selectively coupled to an output. The respective variable gain stages and variable level shifters can be adjusted so that an output signal at the output has a desired dynamic range.
摘要翻译：与各种OPU电路一起使用的驱动电路具有单端输入和差分输入。单端输入耦合到具有可变增益级和可变电平转换器的单端信号路径。差分输入耦合到具有可变增益级和可变电平转换器的差分信号路径。单端信号路径和差分信号路径可以选择性地耦合到输出端。可以调节各个可变增益级和可变电平移位器，使得输出端的输出信号具有期望的动态范围。

2. 发明授权

US07133621B1 Optical communication with phase encoding and phase shifting 有权
标题翻译：具有相位编码和相移的光通信
公开(公告)号：US07133621B1
公开(公告)日：2006-11-07
申请号：US10194795
申请日：2002-07-12
申请人： Fu-Tai An
发明人： Fu-Tai An
IPC分类号： H04B10/04
CPC分类号： H04B10/5055 , H04B10/505 , H04B10/5165
摘要： A communication system comprises a phase encoder, a phase shifter, and a modulator. The phase encoder receives user data and phase encodes the user data to form an encoded signal representing the user data. The phase shifter shifts a phase of the encoded signal to generate a phase shifted signal. The modulator receives a first optical signal and modulates the first optical signal with the encoded signal and the phase shifted signal to form an optical single sideband signal representing the user data. The modulator then transmits the optical single sideband signal representing the user data.
摘要翻译：通信系统包括相位编码器，移相器和调制器。相位编码器接收用户数据并对用户数据进行相位编码，以形成表示用户数据的编码信号。移相器移位编码信号的相位以产生相移信号。调制器接收第一光信号并用编码信号和相移信号调制第一光信号以形成表示用户数据的光单边带信号。然后，调制器发送表示用户数据的光学单边带信号。

3. 发明申请

US20120020444A1 Slicing level and sampling phase adaptation circuitry for data recovery systems 有权
标题翻译：用于数据恢复系统的切片级和采样相位适配电路
公开(公告)号：US20120020444A1
公开(公告)日：2012-01-26
申请号：US12929548
申请日：2011-02-01
申请人： Fu-Tai An , Jen-Tai Hsu
发明人： Fu-Tai An , Jen-Tai Hsu
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H04L7/033
摘要： The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.
摘要翻译：本发明为数据恢复系统创建了一个限幅电平和采样相位自适应电路。本发明利用简单的误码率估计技术探讨了眼睛开放的边界，以确定最佳切片电平和采样相位。使用几个协作采样器实现误码率估计。

4. 发明授权

US08633757B1 Low-noise, temperature-insensitive, voltage or current input, analog front end architecture 失效
标题翻译：低噪声，温度不敏感，电压或电流输入，模拟前端架构
公开(公告)号：US08633757B1
公开(公告)日：2014-01-21
申请号：US12713973
申请日：2010-02-26
申请人： Fu-Tai An , Yingxuan Li , Yonghua Song
发明人： Fu-Tai An , Yingxuan Li , Yonghua Song
IPC分类号： H03B1/00 , H03K3/00 , H03K17/14 , H03K17/16
CPC分类号： H03K19/0175 , H03F1/0277 , H03F1/301 , H03F3/195 , H03F3/45475 , H03F3/45928 , H03F2200/447 , H03F2200/451 , H03F2200/453 , H03F2203/45612
摘要： AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.
摘要翻译： AFE电路处理电压和电流输入信号。在一个实施例中，从输入端提供电压路径和电流路径。开关电路选择其中一条路径。开关还接通或关断用于将电流输入转换成电压的电流 - 电压转换电路。在一个实施例中，通过使用用于差分电路的负参考的专用接地引脚或端子来显着降低噪声。这将与输入信号相同的外部板噪声应用于负参考，因此噪声在差分信号中被消除。在一个实施例中，通过IPTAT电路提供温度补偿，IPTAT电路用于向上移动电压，以平衡随着温度升高的直流电压的降低。

5. 发明授权

US07710188B1 Low-noise, temperature-insensitive, voltage or current input, analog front end architecture 失效
标题翻译：低噪声，温度不敏感，电压或电流输入，模拟前端架构
公开(公告)号：US07710188B1
公开(公告)日：2010-05-04
申请号：US11523372
申请日：2006-09-18
申请人： Fu-Tai An , Yingxuan Li , Yonghua Song
发明人： Fu-Tai An , Yingxuan Li , Yonghua Song
IPC分类号： H03K17/687
CPC分类号： H03K19/0175 , H03F1/0277 , H03F1/301 , H03F3/195 , H03F3/45475 , H03F3/45928 , H03F2200/447 , H03F2200/451 , H03F2200/453 , H03F2203/45612
摘要： AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.
摘要翻译： AFE电路处理电压和电流输入信号。在一个实施例中，从输入端提供电压路径和电流路径。开关电路选择其中一条路径。开关还接通或关断用于将电流输入转换成电压的电流 - 电压转换电路。在一个实施例中，通过使用用于差分电路的负参考的专用接地引脚或端子来显着降低噪声。这将与输入信号相同的外部板噪声应用于负参考，因此噪声在差分信号中被消除。在一个实施例中，通过IPTAT电路提供温度补偿，IPTAT电路用于向上移动电压，以平衡随着温度升高的直流电压的降低。

6. 发明授权

US08488731B2 Slicing level and sampling phase adaptation circuitry for data recovery systems 有权
标题翻译：用于数据恢复系统的切片级和采样相位适配电路
公开(公告)号：US08488731B2
公开(公告)日：2013-07-16
申请号：US12929548
申请日：2011-02-01
申请人： Fu-Tai An , Jen-Tai Hsu
发明人： Fu-Tai An , Jen-Tai Hsu
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H04L7/033
摘要： The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.
摘要翻译：本发明为数据恢复系统创建了一个限幅电平和采样相位自适应电路。本发明利用简单的误码率估计技术探讨了眼睛开放的边界，以确定最佳切片电平和采样相位。使用几个协作采样器实现误码率估计。

7. 发明授权

US08331206B1 Calibration based DC coupled analog front end for optical storage system 有权
标题翻译：基于校准的直流耦合模拟前端用于光存储系统
公开(公告)号：US08331206B1
公开(公告)日：2012-12-11
申请号：US12972733
申请日：2010-12-20
申请人： Yingxuan Li , Fu-Tai An , Yonghua Song
发明人： Yingxuan Li , Fu-Tai An , Yonghua Song
IPC分类号： G11B7/00
CPC分类号： G11B7/0945
摘要： In an apparatus for conditioning a signal from an optical pickup unit (OPU), a single-ended channel includes a first signal processing block to calibrate a dark level of a single-ended signal corresponding to a single-ended output of the OPU, if any, and to center the single-ended signal. A dual-ended channel includes a second signal processing block to calibrate a dark level of a dual-ended signal corresponding to a dual-ended output of the OPU, if any, and to center the dual-ended signal. A multiplexer selects one of the single-ended channel and the dual-ended channel, and outputs a selected signal. A digital signal processing stage converts the selected signal to a digital signal.
摘要翻译：在用于调节来自光学拾取单元（OPU）的信号的装置中，单端通道包括第一信号处理块，用于校准对应于OPU的单端输出的单端信号的暗电平，如果任何，并将中心的单端信号。双端通道包括第二信号处理块，用于校准对应于OPU的双端输出的双端信号的暗电平（如果有的话），并使双端信号居中。复用器选择单端信道和双端信道之一，并输出所选信号。数字信号处理级将选择的信号转换为数字信号。

8. 发明授权

US07876147B1 Background offset cancellation scheme for continuous time gm-C filters 有权
标题翻译：连续时间gm-C滤波器的背景偏移消除方案
公开(公告)号：US07876147B1
公开(公告)日：2011-01-25
申请号：US12472229
申请日：2009-05-26
申请人： Fu-Tai An , Xuemei Liu
发明人： Fu-Tai An , Xuemei Liu
IPC分类号： H03K5/00
CPC分类号： H03F3/45183 , H03F3/45179 , H03F3/45982 , H03F3/72 , H03F2200/405 , H03F2203/45586 , H03F2203/45588 , H03F2203/45678 , H03F2203/45681 , H03H11/0472 , H03H2210/015 , H03H2210/021 , H03H2210/04
摘要： The present disclosure describes methods and apparatus for compensating DC offset in a filter having a plurality of transconductance pieces. In one implementation, the method includes measuring a corresponding DC offset associated with each transconductance piece of the plurality of transconductance pieces; storing each measured DC offset corresponding to each transconductance piece of the plurality of transconductance pieces; selecting one or more of the plurality of transconductance pieces to be used during operation of the filter; deriving an aggregate amount of DC offset for the one or more selected transconductance pieces, the aggregate amount of DC offset being derived based on each stored DC offset value corresponding to each selected transconductance piece; and applying the derived aggregate amount of DC offset to the one or more selected transconductance pieces to compensate for the DC offset during the operation of the filter.
摘要翻译：本公开描述了用于补偿具有多个跨导件的滤波器中的DC偏移的方法和装置。在一个实施方案中，该方法包括测量与多个跨导件中的每个跨导片相关联的对应DC偏移; 存储与所述多个跨导片中的每个跨导片相对应的每个测量的DC偏移; 选择在所述过滤器的操作期间使用的所述多个跨导件中的一个或多个; 导出所述一个或多个所选跨导件的DC偏移的总量，基于对应于每个所选跨导件的每个存储的DC偏移值导出DC偏移的总量; 以及将所导出的DC偏移量的总量应用于所述一个或多个选择的跨导片，以补偿在所述滤波器的操作期间的所述DC偏移。

9. 发明授权

US08547149B2 Clock and data recovery system 有权
标题翻译：时钟和数据恢复系统
公开(公告)号：US08547149B2
公开(公告)日：2013-10-01
申请号：US13064520
申请日：2011-03-30
申请人： Fu-Tai An , Jen-Tai Hsu , Yi-Lin Lee
发明人： Fu-Tai An , Jen-Tai Hsu , Yi-Lin Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H04L7/033
摘要： This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.
摘要翻译：本发明提供一种时钟和数据恢复系统，其包括多个gm单元，控制装置，电阻器和电容器。 gm单元分别具有输入端和输出端。控制装置连接到这些输出端。根据时间值，控制装置控制多个gm单元的一部分以形成第一gm单元，并且控制装置控制多个gm单元的另一部分以形成第二gm单元。电阻连接在第一个gm单元和第二个gm单元之间。电容器连接到第二个gm单元。其中，控制装置根据时分复用方式控制第一gm单元和第二gm单元的比率。

10. 发明申请

US20120020203A1 Clock and data recovery system 有权
标题翻译：时钟和数据恢复系统
公开(公告)号：US20120020203A1
公开(公告)日：2012-01-26
申请号：US13064520
申请日：2011-03-30
申请人： Fu-Tai An , Jen-Tai Hsu , Yi-Lin Lee
发明人： Fu-Tai An , Jen-Tai Hsu , Yi-Lin Lee
IPC分类号： H04L12/26
CPC分类号： H03L7/093 , H04L7/033
摘要： This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.
摘要翻译：本发明提供一种时钟和数据恢复系统，其包括多个gm单元，控制装置，电阻器和电容器。 gm单元分别具有输入端和输出端。控制装置连接到这些输出端。根据时间值，控制装置控制多个gm单元的一部分以形成第一gm单元，并且控制装置控制多个gm单元的另一部分以形成第二gm单元。电阻连接在第一个gm单元和第二个gm单元之间。电容器连接到第二个gm单元。其中，控制装置根据时分复用方式控制第一gm单元和第二gm单元的比率。

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