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1. 发明授权

US08488731B2 Slicing level and sampling phase adaptation circuitry for data recovery systems 有权
标题翻译：用于数据恢复系统的切片级和采样相位适配电路
公开(公告)号：US08488731B2
公开(公告)日：2013-07-16
申请号：US12929548
申请日：2011-02-01
申请人： Fu-Tai An , Jen-Tai Hsu
发明人： Fu-Tai An , Jen-Tai Hsu
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H04L7/033
摘要： The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.
摘要翻译：本发明为数据恢复系统创建了一个限幅电平和采样相位自适应电路。本发明利用简单的误码率估计技术探讨了眼睛开放的边界，以确定最佳切片电平和采样相位。使用几个协作采样器实现误码率估计。

2. 发明申请

US20060292739A1 Method and apparatus to boost high-speed I/O signal performance using semi-interleaved transmitter/receiver pairs at silicon die bump and package layout interfaces 有权
标题翻译：在硅芯片凹凸和封装布局界面上使用半交错发射器/接收器对来提高高速I / O信号性能的方法和装置
公开(公告)号：US20060292739A1
公开(公告)日：2006-12-28
申请号：US11170558
申请日：2005-06-28
申请人： Cliff Lee , Scott Gardiner , Jeffrey Krieger , Jen-Tai Hsu , Fei Deng
发明人： Cliff Lee , Scott Gardiner , Jeffrey Krieger , Jen-Tai Hsu , Fei Deng
IPC分类号： H01L21/00 , H01L23/02
CPC分类号： H01L27/0207 , H01L27/118 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic circuit structure containing interleaved copies of a first circuit pattern and a second circuit pattern, each circuit pattern containing a transmitter and a receiver, where transmitters and receivers of the two circuit patterns are positioned so that the two transmitters are adjacent or so that the two receivers are adjacent. Other structures and methods are also described and claimed.
摘要翻译：包含第一电路图案和第二电路图案的交错副本的微电子电路结构，每个电路图案包含发射器和接收器，其中两个电路图案的发射器和接收器被定位成使得两个发射器相邻或使得两个接收器相邻。还描述和要求保护其它结构和方法。

3. 发明授权

US06445316B1 Universal impedance control for wide range loaded signals 有权
标题翻译：用于宽范围加载信号的通用阻抗控制
公开(公告)号：US06445316B1
公开(公告)日：2002-09-03
申请号：US09672604
申请日：2000-09-29
申请人： Jen-Tai Hsu , Andrew M. Volk
发明人： Jen-Tai Hsu , Andrew M. Volk
IPC分类号： H03M148
CPC分类号： H03K19/0005
摘要： In one embodiment of the present invention, a compensation driving circuit includes a code generator, an enable circuit, and a driver. The code generator generates a driver code from a compensation code according to a selector signal. The driver code corresponds to a buffer having an impedance. The enable circuit enables the driver code. The driver controls impedance of the buffer according to the driver code.
摘要翻译：在本发明的一个实施例中，补偿驱动电路包括代码发生器，使能电路和驱动器。代码生成器根据选择器信号从补偿代码生成驱动程序代码。驱动程序代码对应于具有阻抗的缓冲器。启用电路启用驱动程序代码。驱动器根据驱动程序代码控制缓冲器的阻抗。

4. 发明授权

US06507218B1 Method and apparatus for reducing back-to-back voltage glitch on high speed data bus 失效
标题翻译：降低高速数据总线上背对背电压毛刺的方法和装置
公开(公告)号：US06507218B1
公开(公告)日：2003-01-14
申请号：US09540822
申请日：2000-03-31
申请人： Hing Y. To , Jen-Tai Hsu
发明人： Hing Y. To , Jen-Tai Hsu
IPC分类号： H03K190175
CPC分类号： G06F13/4077
摘要： An example embodiment of a method and apparatus for reducing back-to-back voltage glitch on a high speed bus is described. A pre-driver circuit receives an input voltage signal whose voltage level swings from a logically low voltage level to a logically high voltage level where the logically low voltage level approximately equals VSS and the logically high voltage level approximately equals VCC. The pre-driver circuit reduces the magnitude of the voltage swing to create a signal that when delivered to a driver transistor ensures that the driver transistor will operate in its saturation region even when the voltage on the high speed bus is at its minimum specified voltage. When the driver transistor operates in its saturation region it can sink a constant current and provide a high output impedance.
摘要翻译：描述了用于减少高速总线上背对背电压毛刺的方法和装置的示例性实施例。预驱动电路接收输入电压信号，其电压电平从逻辑低电压电平摆动到逻辑高电压电平，其中逻辑低电压电平近似等于VSS，逻辑高电压电平近似等于VCC。预驱动器电路减小电压摆幅的大小，以产生当传送到驱动器晶体管时确保驱动晶体管即使在高速总线上的电压处于其最小指定电压时也将在其饱和区域中工作的信号。当驱动晶体管工作在饱和区域时，它可以吸收恒定电流并提供高输出阻抗。

5. 发明申请

US20120020444A1 Slicing level and sampling phase adaptation circuitry for data recovery systems 有权
标题翻译：用于数据恢复系统的切片级和采样相位适配电路
公开(公告)号：US20120020444A1
公开(公告)日：2012-01-26
申请号：US12929548
申请日：2011-02-01
申请人： Fu-Tai An , Jen-Tai Hsu
发明人： Fu-Tai An , Jen-Tai Hsu
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H04L7/033
摘要： The invention creates a slicing level and sampling phase adaptation circuitry for data recovery systems. The invention explores the boundary of the eye opening to decide the optimal slicing level and sampling phase with a simple bit error rate estimation technique. Bit error rate estimation is achieved with several collaborating samplers.
摘要翻译：本发明为数据恢复系统创建了一个限幅电平和采样相位自适应电路。本发明利用简单的误码率估计技术探讨了眼睛开放的边界，以确定最佳切片电平和采样相位。使用几个协作采样器实现误码率估计。

6. 发明授权

US06556022B2 Method and apparatus for local parameter variation compensation 有权
标题翻译：局部参数变化补偿方法和装置
公开(公告)号：US06556022B2
公开(公告)日：2003-04-29
申请号：US09895290
申请日：2001-06-29
申请人： Thomas To , Jen-Tai Hsu , Andrew M. Volk
发明人： Thomas To , Jen-Tai Hsu , Andrew M. Volk
IPC分类号： G01R2700
CPC分类号： H03K19/00384
摘要： In order to detect performance parameter variations at different locations, local parameter detectors are located at the various local locations. One of the local locations is selected as the reference location while the other local locations are selected as destination locations. The reference location is utilized to determine a reference parameter value, while each destination location compares its local parameter value to the reference parameter value. The parameter values are current encoded and the reference parameter value is sent to the other locations for the comparisons. The comparison at the destination locations each generates a corrective signal to compensate for the difference in the parameter value between the locations. Parameter compensation is provided to reduce performance skew among the distributed locations.
摘要翻译：为了检测不同位置的性能参数变化，本地参数检测器位于各种局部位置。选择其中一个本地位置作为参考位置，而选择其他本地位置作为目标位置。参考位置用于确定参考参数值，而每个目标位置将其本地参数值与参考参数值进行比较。参数值是当前编码的，参考参数值被发送到其他位置进行比较。目的地位置处的比较各自产生校正信号以补偿位置之间的参数值的差异。提供参数补偿以减少分布位置之间的性能偏差。

7. 发明授权

US06313661B1 High voltage tolerant I/O buffer 有权
标题翻译：高耐压I / O缓冲器
公开(公告)号：US06313661B1
公开(公告)日：2001-11-06
申请号：US09540395
申请日：2000-03-31
申请人： Jen-Tai Hsu
发明人： Jen-Tai Hsu
IPC分类号： H03K190175
CPC分类号： H03K19/00315
摘要： An input/output (I/O) buffer having an output node tolerant of an externally applied high voltage signal is powered by a lower voltage supply potential and comprises a n-well region and a bias generation circuit that generates a reference voltage at an internal node. A PMOS pull-up transistor is coupled between the lower voltage supply potential and the output node, and NMOS pull-down transistor is coupled between the output node and a ground reference potential. First and second PMOS charging transistors each of their gates coupled to the internal node, with the first PMOS charging transistor being coupled between the output node and the gate of the PMOS pull-up transistor. The second PMOS charging transistor is coupled between the output node and the n-well region. The first and second charging transistors operate to pass a pad voltage applied to the output node to the gate of the PMOS pull-up transistor and the n-well region, respectively, when the pad voltage reaches or exceeds the lower voltage supply potential.
摘要翻译：具有外部施加的高电压信号的输出节点的输入/输出（I / O）缓冲器由较低电压电源供电，并且包括n阱区域和偏置产生电路，其在内部产生参考电压节点。 PMOS上拉晶体管耦合在低电压电源电压和输出节点之间，并且NMOS下拉晶体管耦合在输出节点和接地参考电位之间。其第一和第二PMOS充电晶体管的每个门耦合到内部节点，其中第一PMOS充电晶体管耦合在输出节点和PMOS上拉晶体管的栅极之间。第二PMOS充电晶体管耦合在输出节点和n阱区之间。当焊盘电压达到或超过较低电压供应电位时，第一和第二充电晶体管分别操作施加到输出节点的焊盘电压到PMOS上拉晶体管和n阱区的栅极。

8. 发明授权

US08547149B2 Clock and data recovery system 有权
标题翻译：时钟和数据恢复系统
公开(公告)号：US08547149B2
公开(公告)日：2013-10-01
申请号：US13064520
申请日：2011-03-30
申请人： Fu-Tai An , Jen-Tai Hsu , Yi-Lin Lee
发明人： Fu-Tai An , Jen-Tai Hsu , Yi-Lin Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/093 , H04L7/033
摘要： This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.
摘要翻译：本发明提供一种时钟和数据恢复系统，其包括多个gm单元，控制装置，电阻器和电容器。 gm单元分别具有输入端和输出端。控制装置连接到这些输出端。根据时间值，控制装置控制多个gm单元的一部分以形成第一gm单元，并且控制装置控制多个gm单元的另一部分以形成第二gm单元。电阻连接在第一个gm单元和第二个gm单元之间。电容器连接到第二个gm单元。其中，控制装置根据时分复用方式控制第一gm单元和第二gm单元的比率。

9. 发明授权

US08400226B2 Oscillation circuit and associated method 有权
标题翻译：振荡电路及相关方法
公开(公告)号：US08400226B2
公开(公告)日：2013-03-19
申请号：US13208539
申请日：2011-08-12
申请人： Yen-Chung Chen , Tsai-Ming Yang , Jen-Tai Hsu
发明人： Yen-Chung Chen , Tsai-Ming Yang , Jen-Tai Hsu
IPC分类号： H03B5/12
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B2200/0048
摘要： An oscillation circuit and associated method, wherein the oscillation circuit provides a pair of oscillation signals at two oscillation nodes, and includes a first capacitor, a switch circuit and a second capacitor serially coupled between the two oscillation nodes; the switch circuit conducts between the first capacitor and the second capacitor on an enable voltage higher than a power voltage of the oscillation circuit.
摘要翻译：一种振荡电路及相关方法，其中振荡电路在两个振荡节点处提供一对振荡信号，并包括串联耦合在两个振荡节点之间的第一电容器，开关电路和第二电容器; 开关电路在高于振荡电路的电源电压的使能电压下在第一电容器和第二电容器之间导通。

10. 发明申请

US20130038399A1 OSCILLATION CIRCUIT AND ASSOCIATED METHOD 有权
标题翻译：振荡电路及相关方法
公开(公告)号：US20130038399A1
公开(公告)日：2013-02-14
申请号：US13208539
申请日：2011-08-12
申请人： Yen-Chung Chen , Tsai-Ming Yang , Jen-Tai Hsu
发明人： Yen-Chung Chen , Tsai-Ming Yang , Jen-Tai Hsu
IPC分类号： H03B5/18
CPC分类号： H03B5/1228 , H03B5/1215 , H03B5/1243 , H03B5/1265 , H03B2200/0048
摘要： An oscillation circuit and associated method, wherein the oscillation circuit provides a pair of oscillation signals at two oscillation nodes, and includes a first capacitor, a switch circuit and a second capacitor serially coupled between the two oscillation nodes; the switch circuit conducts between the first capacitor and the second capacitor on an enable voltage higher than a power voltage of the oscillation circuit.
摘要翻译：一种振荡电路及相关方法，其中振荡电路在两个振荡节点处提供一对振荡信号，并包括串联耦合在两个振荡节点之间的第一电容器，开关电路和第二电容器; 开关电路在高于振荡电路的电源电压的使能电压下在第一电容器和第二电容器之间导通。

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