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1. 发明授权

US08026742B1 Phase detector 有权
标题翻译：相位检测器
公开(公告)号：US08026742B1
公开(公告)日：2011-09-27
申请号：US12860440
申请日：2010-08-20
申请人： Pantas Sutardja , Christopher L. Painter , Yingxuan Li , Qing Yang
发明人： Pantas Sutardja , Christopher L. Painter , Yingxuan Li , Qing Yang
IPC分类号： H03D13/00
CPC分类号： H03D13/00
摘要： In one embodiment, a phase detector is provided comprising a first input, a second input, and first circuitry in communication with the first and second inputs, the first circuitry operative to provide an indication of a phase difference between a first signal supplied by the first input and a second signal supplied by the second input, wherein an aberration in one of the first and second signals results in an incorrect indication of phase difference. The phase detector also comprises second circuitry in communication with the first circuitry, the second circuitry operative to provide a correct indication of phase difference despite the aberration in the at least one of the first and second signals. In another embodiment, a differential phase detector is provided.
摘要翻译：在一个实施例中，提供了一种相位检测器，包括第一输入端，第二输入端和与第一和第二输入端通信的第一电路，第一电路用于提供由第一输入端提供的第一信号之间的相位差的指示，输入和由第二输入提供的第二信号，其中第一和第二信号之一中的像差导致相位差的不正确指示。相位检测器还包括与第一电路通信的第二电路，第二电路可操作以提供相位差的正确指示，尽管第一和第二信号中的至少一个信号中存在像差。在另一个实施例中，提供差分相位检测器。

2. 发明授权

US07881172B1 Flexible optical write strategy 有权
标题翻译：灵活的光写策略
公开(公告)号：US07881172B1
公开(公告)日：2011-02-01
申请号：US12853337
申请日：2010-08-10
申请人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
发明人： Pantas Sutardja , Yingxuan Li , Daniel Mumford
IPC分类号： G11B7/00
CPC分类号： G11B7/126 , G11B7/0062
摘要： A driver includes a parameter generation module configured to generate timing parameters based upon a received bit stream. A timing encoding module is configured to determine a plurality of pulse defining parameters based on the timing parameters. A pulse generation module is configured to determine a plurality of generic pulses based on the plurality of pulse defining parameters. The pulse generation module is configured to combine the plurality of generic pulses into a plurality of enable signals. The pulse generation module is configured to selectively invert a first enable signal of the plurality of enable signals. The pulse generation module is configured to output the plurality of enable signals including the first enable signal to a laser driver.
摘要翻译：驱动器包括被配置为基于接收到的比特流来生成定时参数的参数生成模块。定时编码模块被配置为基于定时参数确定多个脉冲定义参数。脉冲发生模块被配置为基于多个脉冲定义参数来确定多个通用脉冲。脉冲发生模块被配置为将多个通用脉冲组合成多个使能信号。脉冲发生模块被配置为选择性地反转多个使能信号的第一使能信号。脉冲发生模块被配置为向激光驱动器输出包括第一使能信号的多个使能信号。

3. 发明授权

US07242224B1 Continuous, wide-range frequency synthesis and phase tracking methods and apparatus 有权
公开(公告)号：US07242224B1
公开(公告)日：2007-07-10
申请号：US10990216
申请日：2004-11-15
申请人： Yingxuan Li , Pantas Sutardja
发明人： Yingxuan Li , Pantas Sutardja
IPC分类号： H03B21/00
CPC分类号： H03L7/18 , H03L7/0891 , H03L7/091 , H03L7/0991 , H03L7/23
摘要： Circuitry and methods are provided for continuously adjustable frequency synthesis. The synthesis covers a wide range of possible frequencies and can be performed to a high degree of precision. In an embodiment of the invention, an analog phase-locked loop (“PLL”) performs relatively coarse wide-range frequency synthesis, while a digital PLL performs relatively fine narrow-range frequency synthesis and phase alignment. The analog PLL is capable of varying frequency in a stepwise linear fashion. The digital PLL communicates with the analog PLL to ensure that the output of the analog PLL is within the digital PLL's specified pull-in range.

4. 发明授权

US06618786B1 Current-mode bus line driver having increased output impedance 失效
标题翻译：电流模式总线驱动器具有增加的输出阻抗
公开(公告)号：US06618786B1
公开(公告)日：2003-09-09
申请号：US09650430
申请日：2000-08-28
申请人： Stefanos Sidiropoulos , Yingxuan Li
发明人： Stefanos Sidiropoulos , Yingxuan Li
IPC分类号： G06F1314
CPC分类号： G06F13/4086
摘要： A current-mode bus line driver includes a primary current source and a supplemental current source. The primary current source is an open-drain NMOS transistor, whose output current decreases at low output voltages. The supplemental current source is responsive to low output voltages to provide a supplemental output current, in addition to the output current of the primary current source. The supplemental current source consists of an inverter and a current mirror. The inverter produces a correction current that is inversely related to the voltage output of the primary current source. This correction current is amplified by the current mirror to produce the supplemental output current. The current mirror is self-limiting, in that its current output falls off at very low output voltages.
摘要翻译：电流模式总线驱动器包括初级电流源和补充电流源。初级电流源是开漏NMOS晶体管，其输出电流在低输出电压下降低。除了主电流源的输出电流之外，补充电流源响应于低输出电压以提供补充输出电流。补充电流源由逆变器和电流镜组成。逆变器产生与初级电流源的电压输出成反比关系的校正电流。该校正电流由电流镜放大以产生补充输出电流。电流镜是自限制的，因为它的电流输出在非常低的输出电压下降。

5. 发明授权

US08614592B1 High data rate envelope detector for high speed optical storage application 失效
标题翻译：用于高速光存储应用的高数据速率包络检测器
公开(公告)号：US08614592B1
公开(公告)日：2013-12-24
申请号：US12764578
申请日：2010-04-21
申请人： Qiang Luo , Yingxuan Li , Sriharsha Annadore , Pantas Sutardja
发明人： Qiang Luo , Yingxuan Li , Sriharsha Annadore , Pantas Sutardja
IPC分类号： H03K5/153
CPC分类号： G11B20/10009 , G01R19/04 , G11B20/10416 , G11B2220/2516 , G11B2220/2562
摘要： To detect the peaks level of an incoming signal, the difference between the voltage level of the incoming signal and a voltage developed across a capacitor is amplified. The amplified difference signal is applied to a transconductor adapted to vary its output current in response to changes in the amplified difference signal. The variations in the current generated by the transconductor are used to change a current flowing through a current mirror that charges the capacitor. The voltage developed across the capacitor represents the detected peak. The capacitor is discharged to a predefined voltage level during the reset periods. A second amplifier receiving the capacitor voltage is optionally used to develop a voltage across a second capacitor that is not reset and thus carries only the detected peak levels.
摘要翻译：为了检测输入信号的峰值电平，输入信号的电压电平和电容器两端产生的电压之间的差异被放大。放大的差分信号被施加到适于根据放大的差分信号的变化改变其输出电流的跨导体。由跨导体产生的电流的变化用于改变流经电容器的电流镜的电流。电容器上产生的电压表示检测到的峰值。电容器在复位期间被放电到预定的电压电平。可选地，接收电容器电压的第二放大器用于在不复位的第二电容器上产生电压，并因此仅传送检测到的峰值电平。

6. 发明授权

US08599058B1 Data converter with redundancy for error correction in polarity decision 有权
标题翻译：具有冗余的数据转换器，用于极性判定中的纠错
公开(公告)号：US08599058B1
公开(公告)日：2013-12-03
申请号：US13196368
申请日：2011-08-02
申请人： Yingxuan Li
发明人： Yingxuan Li
IPC分类号： H03M1/34
CPC分类号： H03M1/002 , H03M1/00 , H03M1/0607 , H03M1/0678 , H03M1/12 , H03M1/361
摘要： Systems, methods and computer program products for correcting polarity decision associated with a polarity comparator in an analog-to-digital converter are described. The polarity comparator may perform polarity decision to determine whether an analog signal is greater or smaller than zero. If the voltage difference is greater than zero, then the analog signal may be output to other comparators without polarity inversion. If the voltage difference is smaller than zero, then the signal polarity of the analog signal may be inverted before being output to other comparators. One or more redundant comparators also may be used to correct offsets of the polarity comparator to reduced errors associated with the polarity decision.
摘要翻译：描述了用于校正与模拟 - 数字转换器中的极性比较器相关联的极性判定的系统，方法和计算机程序产品。极性比较器可以执行极性判定以确定模拟信号是大于还是小于零。如果电压差大于零，则模拟信号可以输出到其他比较器而不会极性反转。如果电压差小于零，则模拟信号的信号极性可能在输出到其他比较器之前被反相。还可以使用一个或多个冗余比较器来校正极性比较器的偏移以减少与极性判定相关联的误差。

7. 发明授权

US08331206B1 Calibration based DC coupled analog front end for optical storage system 有权
标题翻译：基于校准的直流耦合模拟前端用于光存储系统
公开(公告)号：US08331206B1
公开(公告)日：2012-12-11
申请号：US12972733
申请日：2010-12-20
申请人： Yingxuan Li , Fu-Tai An , Yonghua Song
发明人： Yingxuan Li , Fu-Tai An , Yonghua Song
IPC分类号： G11B7/00
CPC分类号： G11B7/0945
摘要： In an apparatus for conditioning a signal from an optical pickup unit (OPU), a single-ended channel includes a first signal processing block to calibrate a dark level of a single-ended signal corresponding to a single-ended output of the OPU, if any, and to center the single-ended signal. A dual-ended channel includes a second signal processing block to calibrate a dark level of a dual-ended signal corresponding to a dual-ended output of the OPU, if any, and to center the dual-ended signal. A multiplexer selects one of the single-ended channel and the dual-ended channel, and outputs a selected signal. A digital signal processing stage converts the selected signal to a digital signal.
摘要翻译：在用于调节来自光学拾取单元（OPU）的信号的装置中，单端通道包括第一信号处理块，用于校准对应于OPU的单端输出的单端信号的暗电平，如果任何，并将中心的单端信号。双端通道包括第二信号处理块，用于校准对应于OPU的双端输出的双端信号的暗电平（如果有的话），并使双端信号居中。复用器选择单端信道和双端信道之一，并输出所选信号。数字信号处理级将选择的信号转换为数字信号。

8. 发明授权

US08260246B1 Data rate tracking filter 有权
标题翻译：数据速率跟踪过滤器
公开(公告)号：US08260246B1
公开(公告)日：2012-09-04
申请号：US12139979
申请日：2008-06-16
申请人： Yingxuan Li , Qing Yang
发明人： Yingxuan Li , Qing Yang
IPC分类号： H04B1/16
CPC分类号： H03H11/1291 , G11B20/10046 , G11B2220/2516 , G11B2220/2562 , H03H7/0153 , H03H19/008 , H03H2210/046
摘要： The following embodiments relate to an analog filter having an adjustable transfer function for use in a system or circuit that processes a signal having a changing data rate. The transfer function may be adjusted by adjusting the resistance and/or capacitance of components of the analog filter. The analog filter is calibrated based on an optimum operational parameter at a certain data rate, such as a median data rate. The analog filter may be further adjusted as the data rate of the signal changes.
摘要翻译：以下实施例涉及具有可调节传递函数的模拟滤波器，用于处理具有变化的数据速率的信号的系统或电路中。可以通过调整模拟滤波器的组件的电阻和/或电容来调节传递函数。模拟滤波器基于一定数据速率下的最佳操作参数（如中值数据速率）进行校准。随着信号的数据速率的变化，可以进一步调节模拟滤波器。

9. 发明申请

US20050184896A1 Circuit, apparatus and method for improved current distribution of output drivers enabling improved calibration efficiency and accuracy 失效
公开(公告)号：US20050184896A1
公开(公告)日：2005-08-25
申请号：US11114326
申请日：2005-04-26
申请人： Yingxuan Li
发明人： Yingxuan Li
IPC分类号： G11C29/02 , H03M1/66
CPC分类号： G11C29/022 , G11C7/1057 , G11C29/02 , G11C29/028 , G11C2029/5006 , G11C2207/2254
摘要： A circuit, apparatus and method for efficiently and accurately calibrating an output driver current are provided in embodiments of the present invention. In an embodiment of the present invention, a circuit comprises a first digital-to-analog converter (“DAC”) that generates a first current. A first transistor is coupled to the first DAC and generates a first biasing current responsive to the first current. A second DAC is coupled to the first transistor and generates a first control current responsive to the first biasing current. According to an embodiment of the present invention, the first and second DACs are binary weighted control DACs. According to an embodiment of the present invention, the binary weighted values of the second DAC are obtained in response to a calibration signal generated by a controller. According to an embodiment of the present invention, the first DAC is an M-bit DAC and the second DAC is an N-bit DAC, wherein M is less than N. According to an embodiment of the present invention, the circuit is in a memory device and a controller generates calibration signals.

10. 发明授权

US08633757B1 Low-noise, temperature-insensitive, voltage or current input, analog front end architecture 失效
标题翻译：低噪声，温度不敏感，电压或电流输入，模拟前端架构
公开(公告)号：US08633757B1
公开(公告)日：2014-01-21
申请号：US12713973
申请日：2010-02-26
申请人： Fu-Tai An , Yingxuan Li , Yonghua Song
发明人： Fu-Tai An , Yingxuan Li , Yonghua Song
IPC分类号： H03B1/00 , H03K3/00 , H03K17/14 , H03K17/16
CPC分类号： H03K19/0175 , H03F1/0277 , H03F1/301 , H03F3/195 , H03F3/45475 , H03F3/45928 , H03F2200/447 , H03F2200/451 , H03F2200/453 , H03F2203/45612
摘要： AFE circuitry handles both voltage and current input signals. In one embodiment, both a voltage path and a current path are provided from the input. Switching circuitry selects one of the paths. A switch also turns on or off a current-to-voltage conversion circuit used to convert a current input into a voltage. In one embodiment, noise is significantly reduced by using a dedicated ground pin or terminal for the negative reference of a differential circuit. This applies the same external board noise, which is on the input signal, to the negative reference, so the noise is canceled in the differential signal. In one embodiment, temperature compensation is provided via an IPTAT circuit which is used to shift the voltage up in order to balance the decrease in DC voltage with increasing temperature.
摘要翻译： AFE电路处理电压和电流输入信号。在一个实施例中，从输入端提供电压路径和电流路径。开关电路选择其中一条路径。开关还接通或关断用于将电流输入转换成电压的电流 - 电压转换电路。在一个实施例中，通过使用用于差分电路的负参考的专用接地引脚或端子来显着降低噪声。这将与输入信号相同的外部板噪声应用于负参考，因此噪声在差分信号中被消除。在一个实施例中，通过IPTAT电路提供温度补偿，IPTAT电路用于向上移动电压，以平衡随着温度升高的直流电压的降低。

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