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1. 发明授权

US08390352B2 Apparatus and method for compensating for process, voltage, and temperature variation of the time delay of a digital delay line 有权
标题翻译：用于补偿数字延迟线的时间延迟的过程，电压和温度变化的装置和方法
公开(公告)号：US08390352B2
公开(公告)日：2013-03-05
申请号：US12418981
申请日：2009-04-06
申请人： James Seefeldt , Xiaoxin Feng , Weston Roper
发明人： James Seefeldt , Xiaoxin Feng , Weston Roper
IPC分类号： H03L7/00
CPC分类号： G11C29/022 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4072 , G11C11/4093 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
摘要翻译：提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。补偿电路包括两个延迟线，每个延迟线提供延迟输出。两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。延迟线的数量可能在两个延迟线之间不同。延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM，处理器或其他时钟电路。

2. 发明授权

US08355478B1 Circuit for aligning clock to parallel data 有权
标题翻译：将时钟对准并行数据的电路
公开(公告)号：US08355478B1
公开(公告)日：2013-01-15
申请号：US12475414
申请日：2009-05-29
申请人： James Douglas Seefeldt , Weston Roper , James Hansen
发明人： James Douglas Seefeldt , Weston Roper , James Hansen
IPC分类号： H04L7/033
CPC分类号： H03L7/08
摘要： Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.
摘要翻译：描述了将时钟信号对准并行数据的方法和系统。根据一个实施例，时钟移位电路相对于输入数据信号移动输入时钟信号，并且数据时钟电路使用移位时钟信号重新锁定输入数据信号。时钟转换电路可以包括与多个D触发器（DFF）串联连接的锁相环（PLL）。分数组合逻辑可以设置在该系列中的DFF之间。数据时钟电路可以包括一个DFF以重新锁定每个输入数据位，一对DFF以重新锁定每个输入数据位，或其他电路，例如真实补码块，以用作混频器的本地振荡器。可以产生多个移位时钟信号，例如相对于输入时钟信号偏移60,90,120,180,240和270度的移位时钟信号。

3. 发明申请

US20100308878A1 AUTOMATIC CONTROL OF CLOCK DUTY CYCLE 有权
标题翻译：时钟周期的自动控制
公开(公告)号：US20100308878A1
公开(公告)日：2010-12-09
申请号：US12455572
申请日：2009-06-03
申请人： Xiaoxin Feng , Weston Roper , James D. Seefeldt
发明人： Xiaoxin Feng , Weston Roper , James D. Seefeldt
IPC分类号： H03L7/06 , H03K5/04
CPC分类号： H03K5/156
摘要： In general, this disclosure is directed to a duty cycle correction (DCC) circuit that adjusts a falling edge of a clock signal to achieve a desired duty cycle. In some examples, the DCC circuit may generate a pulse in response to a falling edge of an input clock signal, delay the pulse based on a control voltage, adjust the falling edge of the input clock signal based on the delayed pulse to produce an output clock signal, and adjust the control voltage based on the difference between a duty cycle of the output clock signal and a desired duty cycle. Since the DCC circuit adjusts the falling edge of the clock cycle to achieve a desired duty cycle, the DCC may be incorporated into existing PLL control loops that adjust the rising edge of a clock signal without interfering with the operation of such PLL control loops.
摘要翻译：通常，本公开涉及一种调整时钟信号的下降沿以实现期望的占空比的占空比校正（DCC）电路。在一些示例中，DCC电路可以响应于输入时钟信号的下降沿产生脉冲，基于控制电压延迟脉冲，基于延迟的脉冲调整输入时钟信号的下降沿以产生输出时钟信号，并且基于输出时钟信号的占空比与期望的占空比之间的差来调节控制电压。由于DCC电路调整时钟周期的下降沿以实现期望的占空比，所以DCC可以被并入现有的PLL控制环路中，该PLL控制环路调整时钟信号的上升沿，而不会干扰这种PLL控制环路的操作。

4. 发明申请

US20070103965A1 Memory cell with a vertically integrated delay element 审中-公开
标题翻译：具有垂直集成延迟元件的存储单元
公开(公告)号：US20070103965A1
公开(公告)日：2007-05-10
申请号：US11268007
申请日：2005-11-07
申请人： Weston Roper
发明人： Weston Roper
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A method and device for a vertically integrated delay element are presented. The vertically integrated delay element includes a portion of an interconnect sandwich. The interconnect sandwich includes dielectric layers and metal layers. The portion of the interconnect sandwich is used to form a capacitor, such as a Metal Insulator Metal (MIM) capacitor, in one or more of the dielectric and metal layers of the interconnect sandwich. The capacitor increases the RC delay time of the delay element. The capacitor is also coupled to a Field Effect Transistor (FET). The FET has an increased drain resistance that may be used to further increase the RC delay of the delay element.
摘要翻译：提出了一种用于垂直集成的延迟元件的方法和装置。垂直集成的延迟元件包括互连夹层的一部分。互连夹层包括电介质层和金属层。互连夹层的部分用于在互连夹层的一个或多个介电层和金属层中形成诸如金属绝缘体金属（MIM）电容器的电容器。电容增加了延迟元件的RC延迟时间。电容器也耦合到场效应晶体管（FET）。 FET具有增加的漏极电阻，其可用于进一步增加延迟元件的RC延迟。

5. 发明授权

US06900663B1 Low voltage differential signal driver circuit and method 有权
标题翻译：低压差分信号驱动电路及方法
公开(公告)号：US06900663B1
公开(公告)日：2005-05-31
申请号：US10288003
申请日：2002-11-04
申请人： Weston Roper , Xiaoxin Feng
发明人： Weston Roper , Xiaoxin Feng
IPC分类号： H03K19/094
CPC分类号： H04L25/028
摘要： Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.
摘要翻译：本发明的实施例涉及一种低电压差分信号驱动器（LVDS）电路，其包括电流源，用于控制驱动器输出的逻辑控制开关，耦合在电路两端的电子负载电路和耦合到共模电阻器反馈电路跨过电路，与RC负载并联，用于调整驱动器的阻抗。驱动器能够在没有运算放大器的情况下运行，并在1.8 V电源电压下实现最佳性能。

6. 发明申请

US20100253406A1 APPARATUS AND METHOD FOR COMPENSATING FOR PROCESS, VOLTAGE, AND TEMPERATURE VARIATION OF THE TIME DELAY OF A DIGITAL DELAY LINE 有权
标题翻译：用于补偿数字延迟线时间延迟的过程，电压和温度变化的装置和方法
公开(公告)号：US20100253406A1
公开(公告)日：2010-10-07
申请号：US12418981
申请日：2009-04-06
申请人： James Seefeldt , Xiaoxin Feng , Weston Roper
发明人： James Seefeldt , Xiaoxin Feng , Weston Roper
IPC分类号： H03L1/00 , H03L7/00 , G01R25/00
CPC分类号： G11C29/022 , G11C7/04 , G11C7/1057 , G11C7/1066 , G11C7/222 , G11C11/4072 , G11C11/4093 , G11C29/023 , G11C29/028 , H03K5/133 , H03K2005/00097 , H03K2005/00123 , H03K2005/0013 , H03K2005/00143
摘要： A process, voltage, and temperature (PVT) compensation circuit and a method of continuously generating a delay measure are provided. The compensation circuit includes two delay lines, each delay line providing a delay output. The two delay lines may each include a number of delay elements, which in turn may include one or more current-starved inverters. The number of delay lines may differ between the two delay lines. The delay outputs are provided to a combining circuit that determines an offset pulse based on the two delay outputs and then averages the voltage of the offset pulse to determine a delay measure. The delay measure may be one or more currents or voltages indicating an amount of PVT compensation to apply to input or output signals of an application circuit, such as a memory-bus driver, dynamic random access memory (DRAM), a synchronous DRAM, a processor or other clocked circuit.
摘要翻译：提供过程，电压和温度（PVT）补偿电路以及连续生成延迟测量的方法。补偿电路包括两个延迟线，每个延迟线提供延迟输出。两个延迟线可以各自包括多个延迟元件，延迟元件又包括一个或多个当前饥饿的逆变器。延迟线的数量可能在两个延迟线之间不同。延迟输出被提供给组合电路，该组合电路基于两个延迟输出确定偏移脉冲，然后平均偏移脉冲的电压以确定延迟测量。延迟测量可以是指示应用于应用电路的输入或输出信号的PVT补偿量的一个或多个电流或电压，诸如存储器总线驱动器，动态随机存取存储器（DRAM），同步DRAM，处理器或其他时钟电路。

7. 发明授权

US06609427B1 Gas fill system in a pressure transmitter 有权
标题翻译：压力变送器中的气体填充系统
公开(公告)号：US06609427B1
公开(公告)日：2003-08-26
申请号：US09667289
申请日：2000-09-22
申请人： Brian L. Westfield , Robert C. Hedtke , Weston Roper , Mark C. Fandrey , Roger L. Frick , Scott D. Nelson , Theodore H. Schnaare , Steven M. Behm , Mark S. Schumacher
发明人： Brian L. Westfield , Robert C. Hedtke , Weston Roper , Mark C. Fandrey , Roger L. Frick , Scott D. Nelson , Theodore H. Schnaare , Steven M. Behm , Mark S. Schumacher
IPC分类号： G01L900
CPC分类号： G01D1/00 , G01L13/026 , G01L19/0084 , G01L19/0663 , G01L19/069 , G01L19/083 , H01R13/527 , H01R29/00 , Y10S439/912 , Y10T29/49002
摘要： A pressure transmitter with a hermetically sealed housing surrounding a cavity that is filled with a gas that is free of integrated circuit contaminants. A sensor circuit including an integrated circuit is placed in the cavity and a gas fill port on the housing is sealed. The sensor circuit is electrically adjustable from outside the pressure transmitter and the integrated circuit is protected from contaminated atmospheres outside the pressure transmitter.
摘要翻译：一个压力变送器，带有密封的壳体，围绕一个空腔，充满了没有集成电路污染物的气体。包括集成电路的传感器电路被放置在空腔中，并且壳体上的气体填充口被密封。传感器电路可以从压力变送器外面进行电气调节，并且集成电路可以防止压力变送器外的污染环境。

8. 发明授权

US06568279B2 Scalable process transmitter 有权
公开(公告)号：US06568279B2
公开(公告)日：2003-05-27
申请号：US10125286
申请日：2002-04-18
申请人： Steven M. Behm , Dale S. Davis , Mark C. Fandrey , Roger L. Frick , Robert C. Hedtke , Richard L. Nelson , Scott D. Nelson , Weston Roper , Theodore H. Schnaare , John P. Schulte , Mark S. Schumacher
发明人： Steven M. Behm , Dale S. Davis , Mark C. Fandrey , Roger L. Frick , Robert C. Hedtke , Richard L. Nelson , Scott D. Nelson , Weston Roper , Theodore H. Schnaare , John P. Schulte , Mark S. Schumacher
IPC分类号： G01L700
CPC分类号： G01D1/00 , G01L13/026 , G01L19/0084 , G01L19/0663 , G01L19/069 , G01L19/083 , H01R13/527 , H01R29/00 , Y10S439/912 , Y10T29/49002
摘要： A scalable process transmitter architecture includes a unitized sensor module and an optional scalable transmitter. The sensor module has a sensor output that is configurable which can connect locally to a scalable transmitter module to form a transmitter, or can be wired directly to a remote receiver. The scalable transmitter can mount on the unitized sensor module and generates a scalable output for a remote receiver. The transmitter module can provide more advanced features for specific applications.

9. 发明授权

US06487912B1 Preinstallation of a pressure sensor module 有权
标题翻译：安装压力传感器模块
公开(公告)号：US06487912B1
公开(公告)日：2002-12-03
申请号：US09519912
申请日：2000-03-07
申请人： Steven M. Behm , Richard L. Nelson , Robert Hedtke , Roger Frick , Scott D. Nelson , Mark Fandrey , Theodore H. Schnaare , Brian L. Westfield , Mark S. Schumacher , Weston Roper
发明人： Steven M. Behm , Richard L. Nelson , Robert Hedtke , Roger Frick , Scott D. Nelson , Mark Fandrey , Theodore H. Schnaare , Brian L. Westfield , Mark S. Schumacher , Weston Roper
IPC分类号： G01L900
CPC分类号： G01L19/0046 , G01D1/00 , G01L19/0084 , G01L19/0663 , G01L19/141 , H01R29/00
摘要： A pressure sensor module and method for pre-installation without a converter module. The pressure sensor module is hermetically sealed and can remain undamaged in an installation environment without a converter module. The pressure sensor module can be assembled later with a converter module in the installation environment. The pressure sensor module includes an isolator, a pressure sensor and a circuit that provides a bus for energization, control and a digital pressure output. The bus is connected to contacts in an insulating feedthrough. An integrally formed hermetic external support structure surrounds the pressure sensor and circuit. The hermetic external support structure has a threaded process fluid inlet around the isolator, and a threaded support sleeve supporting the feedthrough.
摘要翻译：压力传感器模块和方法，用于在没有转换器模块的情况下预安装。压力传感器模块是密封的，并且可以在没有转换器模块的安装环境中保持不损坏。以后可以在安装环境中使用转换器模块组装压力传感器模块。压力传感器模块包括隔离器，压力传感器和提供用于通电，控制和数字压力输出的总线的电路。总线连接到绝缘馈通中的触点。整体形成的密封外部支撑结构围绕压力传感器和电路。密封的外部支撑结构具有围绕隔离器的螺纹过程流体入口和支撑馈通的螺纹支撑套筒。

10. 发明申请

US20070103961A1 RAM cell with soft error protection using ferroelectric material 审中-公开
标题翻译：使用铁电材料的具有软错误保护的RAM单元
公开(公告)号：US20070103961A1
公开(公告)日：2007-05-10
申请号：US11268006
申请日：2005-11-07
申请人： Weston Roper , Cheisan Yue
发明人： Weston Roper , Cheisan Yue
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/4125
摘要： A static random access memory (SRAM) cell with single event and soft error protection using ferroelectric material is presented. The SRAM cell comprises two inverters in a mutual feedback loop, with the output of each of the inverters coupled to the input of the other. A ferroelectric capacitor is coupled to the output of one of the inverters in order to induce an RC delay and provide single event upset (SEU), single event effect (SEE), single event transient (SET), and soft error protection. In addition, a method is presented where ferroelectric capacitor of the system is fabricated after the underlayers of the SRAM cell have been implemented in order to avoid substantial changes to standard underlayer processing.
摘要翻译：介绍了使用铁电材料的单事件和软错误保护的静态随机存取存储器（SRAM）单元。 SRAM单元包括互反馈环路中的两个反相器，每个反相器的输出耦合到另一个的输入端。铁电电容器耦合到一个逆变器的输出端，以引起RC延迟，并提供单次事件不平衡（SEU），单事件效应（SEE），单事件瞬态（SET）和软错误保护。另外，在SRAM单元的底层已被实现以避免对标准底层处理的实质性改变之后，制造了系统的铁电电容器的方法。

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