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1. 发明申请

US20160216327A1 FLEXIBLE INTERFACE 审中-公开
标题翻译：柔性接口
公开(公告)号：US20160216327A1
公开(公告)日：2016-07-28
申请号：US15026585
申请日：2014-10-03
申请人： STMICROELECTRONIC (RESEARCH & DEVELOPMENT) LIMITED
发明人： Leonardo NAPOLITANO , Stephen FIRTH
IPC分类号： G01R31/3177 , G06F9/30
CPC分类号： G01R31/3177 , G01R31/31723 , G01R31/318561 , G01R31/318572 , G06F9/30101 , G06F9/3016
摘要： A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.
摘要翻译：在具有多个核的一个或多个配套芯片上提供系统和方法。每个核心具有核心电路和用于进行与核心电路相关的测试的测试接口。测试接口具有一个地址寄存器来保存核心和地址确定电路的地址。地址确定电路被配置为将地址线上接收的地址与保存在地址寄存器中的地址进行比较，以确定核心是否被寻址。地址确定电路还被配置为引导测试接口响应于该确定来执行测试操作。

2. 发明授权

US09194913B2 Circuit and method for diagnosing scan chain failures 有权
标题翻译：用于诊断扫描链失败的电路和方法
公开(公告)号：US09194913B2
公开(公告)日：2015-11-24
申请号：US14033536
申请日：2013-09-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/3185 , G01R31/3177
CPC分类号： G01R31/318541 , G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318561
摘要： A circuit includes a plurality of scan chains each including a plurality of scan blocks. Each scan block includes a storage element and a switching device having an output directly coupled to an input of the storage element. The switching device has a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed and a second input configured to receive one of a function logic output signal or a scan input signal. The switching device is configured to selectively couple the first input or the second input to the input of the storage element.
摘要翻译：电路包括多个扫描链，每条扫描链包括多个扫描块。每个扫描块包括存储元件和具有直接耦合到存储元件的输入的输出的开关器件。开关装置具有第一输入，其被配置为接收来自与其中设置开关装置的扫描链不同的扫描链中的存储元件的输出，以及被配置为接收功能逻辑输出信号或扫描输入中的一个的第二输入信号。开关装置被配置为将第一输入或第二输入选择性地耦合到存储元件的输入。

3. 发明申请

US20150089313A1 HIERARCHICAL ACCESS OF TEST ACCESS PORTS IN EMBEDDED CORE INTEGRATED CIRCUITSGB 审中-公开
标题翻译：嵌入式核心集成电路中测试访问端口的分层访问
公开(公告)号：US20150089313A1
公开(公告)日：2015-03-26
申请号：US14559305
申请日：2014-12-03
申请人： Texas Instruments Incorporated
发明人： Lee D. Whetsel
IPC分类号： G01R31/3177
CPC分类号： G01R31/3177 , G01R31/318555 , G01R31/318558 , G01R31/318561 , G01R31/318563 , G01R31/318572
摘要： An integrated circuit can have plural core circuits, each having a test access port that is defined in IEEE standard 1149.1. Access to and control of these ports is though a test linking module. The test access ports on an integrated circuit can be arranged in a hierarchy with one test linking module controlling access to plural secondary test linking modules and test access ports. Each secondary test linking module in turn can also control access to tertiary test linking modules and test access ports. The test linking modules can also be used for emulation.
摘要翻译：集成电路可以具有多个核心电路，每个核心电路具有在IEEE标准1149.1中定义的测试访问端口。这些端口的访问和控制是一个测试链接模块。集成电路上的测试访问端口可以以一个测试链接模块来控制对多个辅助测试链接模块和测试访问端口的访问的层次结构。每个次级测试链接模块依次也可以控制对三级测试链接模块和测试访问端口的访问。测试链接模块也可用于仿真。

4. 发明授权

US08732540B2 Semiconductor device having input/output wrappers, and a method of controlling the wrappers 有权
标题翻译：具有输入/输出封装的半导体器件，以及控制封装器的方法
公开(公告)号：US08732540B2
公开(公告)日：2014-05-20
申请号：US13107123
申请日：2011-05-13
申请人： JongPil Lee , JaeYoung Lee , Mookyung Kang
发明人： JongPil Lee , JaeYoung Lee , Mookyung Kang
IPC分类号： G01R31/28
CPC分类号： G01R31/318572 , G01R31/318561 , H03K19/17744
摘要： A semiconductor device include a first wrapper including a first scan flip-flop, first control flip-flops and a first pad, the first scan flip-flop receiving a first value and second values and storing the second value for determining a function of the first pad; a second wrapper including a second scan flip-flop, second control flip-flops and a second pad, the second scan flip-flop receiving the first value from the first wrapper and storing the first value for determining a function of the second pad; and an input/output controller configured to provide a shift input signal having the first and second values to the first wrapper.
摘要翻译：一种半导体器件包括：第一封装件，包括第一扫描触发器，第一控制触发器和第一焊盘，第一扫描触发器接收第一值和第二值，并存储用于确定第一值的功能的第二值垫; 包括第二扫描触发器，第二控制触发器和第二焊盘的第二封装件，所述第二扫描触发器从所述第一封装件接收所述第一值，并存储所述第一值以确定所述第二焊盘的功能; 以及输入/输出控制器，被配置为向第一包装提供具有第一和第二值的移位输入信号。

5. 发明授权

US08666690B2 Heterogeneous multi-core integrated circuit and method for debugging same 有权
标题翻译：异构多核集成电路及其调试方法
公开(公告)号：US08666690B2
公开(公告)日：2014-03-04
申请号：US13269574
申请日：2011-10-08
申请人： Amar Nath Deogharia , Robert N. Ehrlich , Robert A. McGowan
发明人： Amar Nath Deogharia , Robert N. Ehrlich , Robert A. McGowan
IPC分类号： G01R27/28
CPC分类号： G01R31/318561 , G01R31/318555 , G06F11/3656
摘要： A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.
摘要翻译：异构多核集成电路包括第一和第二组处理器核心和相应的第一和第二测试访问端口（TAP）。第一和第二TAP通过对应的第一和第二TAP控制器连接到对应的第一和第二调试端口。调试控制电路连接在第一和第二TAP控制器与第一和第二调试端口之间。基于外部配置信号，调试控制电路根据预定的配置模式配置第一和第二TAP控制器与第一和第二调试端口之间的连接，这允许调试异构多核集成电路的灵活性。

6. 发明授权

US08566657B2 Circuit and method for diagnosing scan chain failures 有权
标题翻译：用于诊断扫描链失败的电路和方法
公开(公告)号：US08566657B2
公开(公告)日：2013-10-22
申请号：US13093942
申请日：2011-04-26
申请人： Sandeep Kumar Goel
发明人： Sandeep Kumar Goel
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/3177 , G01R31/318536 , G01R31/318544 , G01R31/318561
摘要： A method includes shifting a first logic sequence into a first scan chain having a first plurality of scan blocks coupled together, outputting a second logic sequence from each of the plurality of scan blocks in the first scan chain to a respective scan block in a second scan chain, and shifting a third logic sequence out of the second scan chain. At least one improperly functioning scan block of the first scan chain is identified based on the third logic sequence shifted out of the second scan chain.
摘要翻译：一种方法包括将第一逻辑序列移动到具有耦合在一起的第一多个扫描块的第一扫描链中，将第一扫描链中的多个扫描块中的每一个的第二逻辑序列输出到第二扫描中的相应扫描块并且将第三逻辑序列移出第二扫描链。基于从第二扫描链中移出的第三逻辑序列来识别第一扫描链的至少一个不正常功能的扫描块。

7. 发明申请

US20130139014A1 VERIFYING AND DETECTING BOUNDARY SCAN CELLS TO INPUT/OUTPUT MAPPING 失效
标题翻译：验证和检测边界扫描单元到输入/输出映射
公开(公告)号：US20130139014A1
公开(公告)日：2013-05-30
申请号：US13305498
申请日：2011-11-28
申请人： Benedikt Geukes , Matteo Michel , Carsten Schmitt , Manfred H. Walz
发明人： Benedikt Geukes , Matteo Michel , Carsten Schmitt , Manfred H. Walz
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318572 , G01R31/318561
摘要： In some embodiments, a computer-implemented method includes receiving, in a processor, a device description code identifying components of a device and connections between the components, wherein some of the components and connections form boundary cells used for testing the device. The method can include processing, in the processor, the device description code to determine that the components and the connections meet a standard governing components and connections necessary for the boundary cells. The method can also include traversing the connections between the components to determine that the connections meet the standard, and reporting, via one or more output devices, that the device complies with the standard.
摘要翻译：在一些实施例中，计算机实现的方法包括在处理器中接收识别设备的组件和组件之间的连接的设备描述代码，其中组件和连接中的一些形成用于测试设备的边界单元。该方法可以包括在处理器中处理设备描述码以确定组件和连接满足边界单元所必需的标准控制组件和连接。该方法还可以包括遍历组件之间的连接以确定连接符合标准，并且经由一个或多个输出设备报告设备符合标准。

8. 发明申请

US20130090887A1 HETEROGENEOUS MULTI-CORE INTEGRATED CIRCUIT AND METHOD FOR DEBUGGING SAME 有权
标题翻译：异质多核集成电路及其调试方法
公开(公告)号：US20130090887A1
公开(公告)日：2013-04-11
申请号：US13269574
申请日：2011-10-08
申请人： Amar Nath Deogharia , Robert N. Ehrlich , Robert A. McGowan
发明人： Amar Nath Deogharia , Robert N. Ehrlich , Robert A. McGowan
IPC分类号： G06F19/00 , G01R31/319
CPC分类号： G01R31/318561 , G01R31/318555 , G06F11/3656
摘要： A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.
摘要翻译：异构多核集成电路包括第一和第二组处理器核心和相应的第一和第二测试访问端口（TAP）。第一和第二TAP通过对应的第一和第二TAP控制器连接到对应的第一和第二调试端口。调试控制电路连接在第一和第二TAP控制器与第一和第二调试端口之间。基于外部配置信号，调试控制电路根据预定的配置模式配置第一和第二TAP控制器与第一和第二调试端口之间的连接，这允许调试异构多核集成电路的灵活性。

9. 发明授权

US07689884B2 Multicore chip test 有权
标题翻译：多芯片测试
公开(公告)号：US07689884B2
公开(公告)日：2010-03-30
申请号：US11789269
申请日：2007-04-23
申请人： Markus Seuring
发明人： Markus Seuring
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318561 , G01R31/318563
摘要： An integrated chip architecture is provided which allows for efficiently testing multiple cores included in the integrated chip architecture. In particular, the provided approach enables the test time and the number of required Input/Output test pins is nearly independent from the number of cores included in the multicore chip. The presented embodiments provide a multicore chip architecture which allows for providing input data to the multiple cores in parallel for simultaneously testing the multiple cores, and analyzing the resulting multiple test outputs on chip. As a result of this analysis embodiments may store on chip an indication for those cores that have not successfully passed the test.
摘要翻译：提供了集成芯片架构，其允许有效测试集成芯片架构中包含的多个核心。特别地，所提供的方法使得测试时间和所需的输入/输出测试引脚的数量几乎与包含在多核芯片中的核心数量无关。所提出的实施例提供了多芯片架构，其允许并行地向多个核提供输入数据以同时测试多个核，并且分析所得到的多个测试输出。作为该分析的结果，实施例可以在芯片上存储尚未成功通过测试的那些核心的指示。

10. 发明申请

US20090259889A1 TEST DEVICE AND METHOD FOR HIERARCHICAL TEST ARCHITECTURE 有权
标题翻译：用于分层测试架构的测试设备和方法
公开(公告)号：US20090259889A1
公开(公告)日：2009-10-15
申请号：US12324795
申请日：2008-11-26
申请人： Kun-Lun Luo
发明人： Kun-Lun Luo
IPC分类号： G06F11/273
CPC分类号： G01R31/318558 , G01R31/318561 , G01R31/318586
摘要： A test device for a hierarchical test architecture is disclosed. The architecture includes cores for plural test layers, a top-level data register, and a top-level test controller. Cores for each test layer are hierarchical test circuits. The top-level test controller retrieves plural control signals, controls the top-level data register based on first type control signals in the control signals, and controls each core based on second type control signals in the control signals.
摘要翻译：公开了一种用于分级测试架构的测试设备。该架构包括用于多个测试层的核心，顶级数据寄存器和顶级测试控制器。每个测试层的核心是分层测试电路。顶级测试控制器检索多个控制信号，根据控制信号中的第一类型控制信号控制顶级数据寄存器，并根据控制信号中的第二类型控制信号控制每个内核。

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