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1. 发明授权

US09612934B2 Network processor with distributed trace buffers 有权
公开(公告)号：US09612934B2
公开(公告)日：2017-04-04
申请号：US13284289
申请日：2011-10-28
申请人： Bradley D. Dobbie , David H. Asher , Richard E. Kessler
发明人： Bradley D. Dobbie , David H. Asher , Richard E. Kessler
IPC分类号： G06F3/00 , G06F11/34 , G06F13/40 , G06F12/084 , G06F3/16 , G06F1/32 , G06F13/38
CPC分类号： G06F11/3495 , G06F1/3203 , G06F3/16 , G06F11/349 , G06F12/084 , G06F13/385 , G06F13/4022
摘要： A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.

2. 发明授权

US06681295B1 Fast lane prefetching 有权
标题翻译：快速车道预取
公开(公告)号：US06681295B1
公开(公告)日：2004-01-20
申请号：US09652451
申请日：2000-08-31
申请人： Stephen C. Root , Richard E. Kessler , David H. Asher , Brian Lilly
发明人： Stephen C. Root , Richard E. Kessler , David H. Asher , Brian Lilly
IPC分类号： G06F1200
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3832 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be loaded into cache, but is not likely to be needed again in the future, preferably is loaded into the fast lane. Data loaded into the fast lane is earmarked for immediate replacement. Data loaded into the slow lanes preferably is data that may not needed again in the near future. Slow data is kept in cache to permit it to be reused if necessary. The high-performance mechanism of data access in a modem microprocessor is with a prefetch; data is moved, with a special prefetch instruction, into cache prior to its intended use. The prefetch instruction requires less machine resources, than carrying out the same intent with an ordinary load instruction. So, the slow-lane, fast-lane decision is accomplished by having a multiplicity of prefetch instructions. By loading “not likely to be needed again” data into the fast lane, and designating such data for immediate replacement, data in other cache blocks, in the other ways, may not be evicted, and overall system performance is increased.
摘要翻译：计算机系统具有集合关联的多路缓存系统，其中至少一种方式被指定为快速通道，并且剩余方式被指定为慢车道。任何需要加载到缓存中但不太可能再次需要的数据最好被加载到快速通道中。加载到快速通道的数据被指定用于立即更换。加载到慢车道中的数据优选地是在不久的将来可能不再需要的数据。慢数据保存在缓存中，以便在必要时重新使用它。调制解调器微处理器中数据访问的高性能机制具有预取功能; 在预期使用之前，将数据用特殊的预取指令移动到缓存中。预取指令比普通加载指令执行相同的意图要求较少的机器资源。因此，通过具有多个预取指令来实现慢通道，快速通道决定。通过将“不太可能需要再次”的数据加载到快速通道中，并且指定这样的数据以立即替换，以其他方式在其他高速缓存块中的数据可能不被驱逐，并且整体系统性能增加。

3. 发明授权

US07941585B2 Local scratchpad and data caching system 有权
标题翻译：本地暂存器和数据缓存系统
公开(公告)号：US07941585B2
公开(公告)日：2011-05-10
申请号：US11015343
申请日：2004-12-17
申请人： David H. Asher , David A. Carlson , Richard E. Kessler
发明人： David H. Asher , David A. Carlson , Richard E. Kessler
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/084 , G06F9/30014 , G06F9/30138 , G06F9/383 , G06F11/3632 , G06F12/0804 , G06F12/0813 , G06F12/0815 , G06F12/0835 , G06F12/0875 , G06F12/0891 , G06F13/24 , G06F2212/6012 , G06F2212/6022
摘要： A RISC-type processor includes a main register file and a data cache. The data cache can be partitioned to include a local memory, the size of which can be dynamically changed on a cache block basis while the processor is executing instructions that use the main register file. The local memory can emulate as an additional register file to the processor and can reside at a virtual address. The local memory can be further partitioned for prefetching data from a non-cacheable address to be stored/loaded into the main register file.
摘要翻译： RISC型处理器包括主寄存器文件和数据高速缓存。可以将数据高速缓存分割成包括本地存储器，当处理器正在执行使用主寄存器文件的指令时，可以在缓存块的基础上动态地改变其大小。本地存储器可以作为额外的寄存器文件模拟到处理器，并且可以驻留在虚拟地址处。本地存储器可以被进一步分区以从不可缓存地址预取数据以被存储/加载到主寄存器文件中。

4. 发明授权

US06212493B1 Profile directed simulation used to target time-critical crossproducts during random vector testing 有权
标题翻译：用于在随机向量测试期间针对时间关键交叉产品的轮廓定向模拟
公开(公告)号：US06212493B1
公开(公告)日：2001-04-03
申请号：US09203119
申请日：1998-12-01
申请人： James D. Huggins , David H. Asher , James B. Keller
发明人： James D. Huggins , David H. Asher , James B. Keller
IPC分类号： G06F11263
CPC分类号： G06F11/263 , G06F11/2236
摘要： A technique for verification of a complex integrated circuit design, such as a microprocessor, using a randomly generated test program to simulate internal events and to determine the timing of external events. The simulation proceeds in two passes. During a first pass, the randomly generated test program and data vectors are applied to a simulation model of the design being verified. During this first pass, an internal agent collects profile data about internal events such as addresses and program counter contents as they occur. During a second pass of the process, the profile data is used to generate directed external events based upon the data observed during the first pass. In this manner, the advantages of rapid test vector generation provided through random schemes is achieved at the same time that a more directed external event correlation is accomplished.
摘要翻译：用于验证诸如微处理器的复杂集成电路设计的技术，其使用随机生成的测试程序来模拟内部事件并确定外部事件的定时。仿真进行两遍。在第一次通过期间，将随机生成的测试程序和数据向量应用于被验证的设计的仿真模型。在第一次通过期间，内部代理收集有关内部事件的配置文件数据，例如地址和程序计数器内容。在该过程的第二次通过期间，轮廓数据用于基于在第一遍期间观察到的数据来生成定向的外部事件。以这种方式，通过随机方案提供的快速测试向量生成的优点在实现更有针对性的外部事件相关性的同时实现。

5. 发明授权

US07370151B2 Method and system for absorbing defects in high performance microprocessor with a large n-way set associative cache 有权
标题翻译：用大型n路组合关联缓存来吸收高性能微处理器缺陷的方法和系统
公开(公告)号：US07370151B2
公开(公告)日：2008-05-06
申请号：US10690137
申请日：2003-10-21
申请人： David H. Asher , Brian Lilly , Joel Grodstein , Patrick M. Fitzgerald
发明人： David H. Asher , Brian Lilly , Joel Grodstein , Patrick M. Fitzgerald
IPC分类号： G06F13/00
CPC分类号： G11C29/76 , G06F12/0864 , G11C15/00
摘要： A method and architecture for improving the usability and manufacturing yield of a microprocessor having a large on-chip n-way set associative cache. The architecture provides a method for working around defects in the portion of the die allocated to the data array of the cache. In particular, by adding a plurality of muxes to a way or ways in the data array of an associative cache having the shorter paths to the access control logic, each way in a bank can be selectively replaced or remapped to the ways with the shorter paths without adding any latency to the system. This selective remapping of separate ways in individual banks of the set associative cache provides a more efficient way to absorb defects and allows more defects to be absorbed in the data array of a set associative cache.
摘要翻译：一种用于提高具有大片上n路组相关高速缓存的微处理器的可用性和制造产量的方法和架构。该架构提供了一种用于处理分配给高速缓存的数据阵列的芯片部分中的缺陷的方法。特别地，通过向具有到访问控制逻辑的较短路径的关联高速缓存的数据阵列中的方式或方式添加多个多路复用器，可以选择性地将存储体中的每个路径替换或重新映射到具有较短路径的路径而不会对系统增加任何延迟。在集合关联高速缓存的各个组中的单独方式的这种选择性重新映射提供了一种更有效的方式来吸收缺陷，并允许在集合关联高速缓存的数据阵列中吸收更多的缺陷。

6. 发明授权

US06918015B2 Scalable directory based cache coherence protocol 失效
标题翻译：基于可扩展目录的缓存一致性协议
公开(公告)号：US06918015B2
公开(公告)日：2005-07-12
申请号：US10403922
申请日：2003-03-31
申请人： Richard E. Kessler , Kourosh Gharachorloo , David H. Asher
发明人： Richard E. Kessler , Kourosh Gharachorloo , David H. Asher
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0817 , G06F12/0828
摘要： A system and method is disclosed to maintain the coherence of shared data in cache and memory contained in the nodes of a multiprocessing computer system. The distributed multiprocessing computer system contains a number of processors each connected to main memory. A processor in the distributed multiprocessing computer system is identified as a Home processor for a memory block if it includes the original memory block and a coherence directory for the memory block in its main memory. An Owner processor is another processor in the multiprocessing computer system that includes a copy of the Home processor memory block in a cache connected to its main memory. Whenever an Owner processor is present for a memory block, it is the only processor in the distributed multiprocessing computer system to contain a copy of the Home processor memory block. Eviction of a memory block copy held by an Owner processor in its cache requires a write of the memory block copy to its Home and update of the corresponding coherence directory. No reads of the Home processor directory or modification of other processor cache and main memory is required. The coherence controller in each processor is able to send and receive messages out of order to maintain the coherence of the shared data in cache and main memory. If an out of order message causes an incorrect next program state, the coherence controller is able to restore the prior correct saved program state and resume execution.
摘要翻译：公开了一种维护多处理计算机系统的节点中包含的高速缓存和存储器中的共享数据的一致性的系统和方法。分布式多处理计算机系统包含多个处理器，每个处理器连接到主存储器。分布式多处理计算机系统中的处理器被识别为用于存储器块的家庭处理器，如果其包括原始存储器块和用于其主存储器中的存储器块的一致性目录。所有者处理器是多处理计算机系统中的另一个处理器，其包括连接到其主存储器的高速缓存中的家庭处理器存储器块的副本。无论何时存在一个内存块的所有者处理器，它是分布式多处理计算机系统中唯一包含家庭处理器内存块副本的处理器。驱逐由所有者处理器在其高速缓存中保存的存储器块副本需要将存储器块副本写入其归属并更新相应的一致性目录。不需要读取家庭处理器目录或修改其他处理器缓存和主内存。每个处理器中的相干控制器能够发送和接收消息，以保持缓存和主存储器中的共享数据的一致性。如果故障信息导致下一个程序状态不正确，则相干控制器能够恢复先前正确保存的程序状态并恢复执行。

7. 发明授权

US08473658B2 Input output bridging 有权
标题翻译：输入输出桥接
公开(公告)号：US08473658B2
公开(公告)日：2013-06-25
申请号：US13280768
申请日：2011-10-25
申请人： Robert A. Sanzone , David H. Asher , Richard E. Kessler
发明人： Robert A. Sanzone , David H. Asher , Richard E. Kessler
IPC分类号： G06F13/00
CPC分类号： G06F13/1605 , G06F13/1684
摘要： In one embodiment, a system comprises a memory, and a first bridge unit for processor access with the memory. The first bridge unit comprises a first arbitration unit that is coupled with an input-output bus, a memory free notification unit (“MFNU”), and the memory, and is configured to receive requests from the input-output bus and receive requests from the MFNU and choose among the requests to send to the memory on a first memory bus. The system further comprises a second bridge unit for packet data access with the memory that includes a second arbitration unit that is coupled with a packet input unit, a packet output unit, and the memory and is configured to receive requests from the packet input unit and receive requests from the packet output unit, and choose among the requests to send to the memory on a second memory bus.
摘要翻译：在一个实施例中，系统包括存储器和用于与存储器进行处理器访问的第一桥接单元。第一桥单元包括与输入输出总线耦合的第一仲裁单元，无存储器通知单元（“MFNU”）和存储器，并且被配置为从输入 - 输出总线接收请求并接收来自 MFNU并在第一条内存总线上选择发送到内存的请求。所述系统还包括用于与所述存储器进行分组数据存取的第二桥单元，所述存储器包括与分组输入单元，分组输出单元和所述存储器耦合的第二仲裁单元，并且被配置为从所述分组输入单元接收请求，从分组输出单元接收请求，并在第二存储器总线上选择发送到存储器的请求。

8. 发明申请

US20130111141A1 MULTI-CORE INTERCONNECT IN A NETWORK PROCESSOR 有权
标题翻译：网络处理器中的多核连接
公开(公告)号：US20130111141A1
公开(公告)日：2013-05-02
申请号：US13285629
申请日：2011-10-31
申请人： Richard E. Kessler , David H. Asher , John M. Perveiler , Bradley D. Dobbie
发明人： Richard E. Kessler , David H. Asher , John M. Perveiler , Bradley D. Dobbie
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/08
摘要： A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.
摘要翻译：网络处理器包括用于处理分组数据的多个处理器核。为了向处理器核提供对存储器子系统的访问，互连电路指导处理器核与L2 Cache和其他存储器件之间的通信。处理器核心分为几组，每组共享一条单独的总线，二级缓存分为多个银行，每个银行都可以访问单独的总线。互连电路处理在多个总线上存储和检索来自处理器核心的数据的请求，并处理从缓存存储器返回数据的响应。因此，网络处理器为多个处理器内核提供高带宽存储器访问。

9. 发明授权

US07606998B2 Store instruction ordering for multi-core processor 有权
标题翻译：存储指令订购多核处理器
公开(公告)号：US07606998B2
公开(公告)日：2009-10-20
申请号：US11002728
申请日：2004-11-30
申请人： David H. Asher , Richard E. Kessler , Yen Lee
发明人： David H. Asher , Richard E. Kessler , Yen Lee
IPC分类号： G06F9/00
CPC分类号： G06F9/3004 , G06F9/30087 , G06F9/3824 , G06F9/3834 , G06F9/3857
摘要： A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue.
摘要翻译：提供了一种用于最小化流水线处理器中的停顿的方法和装置。无序指令调度程序中的指令按顺序执行，而不会通过排序队列将存储数据发送到外部存储器，而不会拖延流水线。

10. 发明授权

US07213087B1 Mechanism to control the allocation of an N-source shared buffer 有权
标题翻译：控制N源共享缓冲区分配的机制
公开(公告)号：US07213087B1
公开(公告)日：2007-05-01
申请号：US09651924
申请日：2000-08-31
申请人： Michael S. Bertone , Richard E. Kessler , David H. Asher , Steve Lang
发明人： Michael S. Bertone , Richard E. Kessler , David H. Asher , Steve Lang
IPC分类号： G06F5/00
CPC分类号： H04L47/39 , H04L49/90
摘要： A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit and memory requests from other processors are delivered to the memory controller by an interprocessor router. The memory controller allocates the memory requests in a shared buffer using a credit-based allocation scheme. The cache control unit and the interprocessor router are each assigned a number of credits. Each must pay a credit to the memory controller when a request is allocated to the shared buffer. If the number of filled spaces in the shared buffer is below a threshold, the buffer immediately returns the credits to the source from which the credit and memory request arrived. If the number of filled spaces in the shared buffer is above a threshold, the buffer holds the credits and returns the credits in a round-robin manner only when a space in the shared buffer becomes free. The number of credits assigned to each source is sufficient to enable each source to deliver an uninterrupted burst of memory requests to the buffer without having to wait for credits to return from the buffer. The threshold is the point when the number of free spaces available in the buffer is equal to the total number of credits assigned to the cache control unit and the interprocessor router.
摘要翻译：一种用于确保公平和有效地使用共享存储器缓冲器的方法和装置。优选实施例包括在多处理器计算机系统中的共享存储器缓冲器。来自本地处理器的存储器请求由高速缓存控制单元传送到本地存储器控制器，并且来自其他处理器的存储器请求由处理器间路由器递送到存储器控制器。存储器控制器使用基于信用的分配方案在共享缓冲器中分配存储器请求。高速缓存控制单元和处理器间路由器分配有多个信用。当请求分配给共享缓冲区时，每个都必须向内存控制器支付抵免额。如果共享缓冲区中的填充空间数量低于阈值，则缓冲区立即将信用返回到信用和存储器请求到达的来源。如果共享缓冲器中的填充空间数目高于阈值，则缓冲器只有当共享缓冲器中的空间变得空闲时才保存信用并以循环方式返回信用。分配给每个源的信用点数量足以使每个源能够将不间断的存储器请求发送到缓冲器，而不必等待信用从缓冲器返回。阈值是缓冲器中可用空间的数量等于分配给缓存控制单元和处理器间路由器的总信用数量的点。

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