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1. 发明授权

US06681295B1 Fast lane prefetching 有权
标题翻译：快速车道预取
公开(公告)号：US06681295B1
公开(公告)日：2004-01-20
申请号：US09652451
申请日：2000-08-31
申请人： Stephen C. Root , Richard E. Kessler , David H. Asher , Brian Lilly
发明人： Stephen C. Root , Richard E. Kessler , David H. Asher , Brian Lilly
IPC分类号： G06F1200
CPC分类号： G06F9/30047 , G06F9/383 , G06F9/3832 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3859 , G06F12/0862 , G06F12/0864 , G06F2212/6028
摘要： A computer system has a set-associative, multi-way cache system, in which at least one way is designated as a fast lane, and remaining way(s) are designated slow lanes. Any data that needs to be loaded into cache, but is not likely to be needed again in the future, preferably is loaded into the fast lane. Data loaded into the fast lane is earmarked for immediate replacement. Data loaded into the slow lanes preferably is data that may not needed again in the near future. Slow data is kept in cache to permit it to be reused if necessary. The high-performance mechanism of data access in a modem microprocessor is with a prefetch; data is moved, with a special prefetch instruction, into cache prior to its intended use. The prefetch instruction requires less machine resources, than carrying out the same intent with an ordinary load instruction. So, the slow-lane, fast-lane decision is accomplished by having a multiplicity of prefetch instructions. By loading “not likely to be needed again” data into the fast lane, and designating such data for immediate replacement, data in other cache blocks, in the other ways, may not be evicted, and overall system performance is increased.
摘要翻译：计算机系统具有集合关联的多路缓存系统，其中至少一种方式被指定为快速通道，并且剩余方式被指定为慢车道。任何需要加载到缓存中但不太可能再次需要的数据最好被加载到快速通道中。加载到快速通道的数据被指定用于立即更换。加载到慢车道中的数据优选地是在不久的将来可能不再需要的数据。慢数据保存在缓存中，以便在必要时重新使用它。调制解调器微处理器中数据访问的高性能机制具有预取功能; 在预期使用之前，将数据用特殊的预取指令移动到缓存中。预取指令比普通加载指令执行相同的意图要求较少的机器资源。因此，通过具有多个预取指令来实现慢通道，快速通道决定。通过将“不太可能需要再次”的数据加载到快速通道中，并且指定这样的数据以立即替换，以其他方式在其他高速缓存块中的数据可能不被驱逐，并且整体系统性能增加。

2. 发明授权

US6163821A Method and apparatus for balancing load vs. store access to a primary data cache 有权
标题翻译：用于平衡负载与对主数据高速缓存的存储访问的方法和装置
公开(公告)号：US6163821A
公开(公告)日：2000-12-19
申请号：US215354
申请日：1998-12-18
申请人： James B. Keller , Richard E. Kessler , Stephen C. Root , Paul Geoffrey Lowney
发明人： James B. Keller , Richard E. Kessler , Stephen C. Root , Paul Geoffrey Lowney
IPC分类号： G06F9/312 , G06F9/38 , G06F13/20 , G06F13/16 , G06F13/362
CPC分类号： G06F9/30043 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.
摘要翻译：计算机方法和装置使得微处理器指令流水线中的加载存储指令分组在适当的时间被中断。计算机方法和装置采用存储器访问部件，当在存储队列中存在先前的存储指令时，周期性地停止发布存储指令。周期性档位偏离问题阶段以发布加载组并存储指令组。在后一种情况下，存储队列可以使用来自先前存储指令的数据来自由地更新数据高速缓存。因此，本发明的存储器访问部件以防止存储队列变满的方式偏移存储指令的发布，并且因此使存储队列在存储队列变满之前写入数据高速缓存。

3. 发明授权

US5146421A High speed parallel multiplier circuit 失效
标题翻译：高速并行乘法电路
公开(公告)号：US5146421A
公开(公告)日：1992-09-08
申请号：US373083
申请日：1989-06-28
申请人： Matthew J. Adiletta , Stephen C. Root
发明人： Matthew J. Adiletta , Stephen C. Root
IPC分类号： G06F7/53 , G06F7/508 , G06F7/52
CPC分类号： G06F7/5318
摘要： The binary multiplier circuit for obtaining a product of an M-bit multiplier and an N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most significant bit position. For every column having three or fewer original summand bits, and having the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most significant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits. The remaining two rows of bits can be input to a two-stage carry-propagating adder circuit to output a sum equal to the product.
摘要翻译：用于获得M位乘法器和N位被乘数乘积的二进制乘法器电路包括产生具有M行和M + N列的原始加法器位矩阵和矩阵减法电路的乘法器电路。在矩阵简化电路中，对于具有三个或更多个原始加法器位的矩阵的每一列，三个位组被输入到全加法器电路中，该加法器电路输出该列的和位和该列的进位位在下一个最高有效位位位置。对于具有三个或更少的原始加和位的列，并且具有尚未减少到两个或更少位的最低有效列位置，两位组被输入到半加法器电路中，该半加法器电路输出该列的和位并携带位在下一个最高有效位位置的列。对于每列，通过对列中的每一组三位使用全加器电路，并通过使用半加法器电路对列中的两位的任何剩余组执行迭代减少。减少继续，直到矩阵的每一列减少到两个或更少位。剩余的两行位可以输入到两级进位传播加法器电路，以输出等于乘积的和。

4. 发明授权

US06911827B2 System and method of measuring low impedances 失效
标题翻译：测量低阻抗的系统和方法
公开(公告)号：US06911827B2
公开(公告)日：2005-06-28
申请号：US10274611
申请日：2002-10-21
申请人： Isaac Kantorovich , Christopher L. Houghton , Stephen C. Root , James J. St. Laurent
发明人： Isaac Kantorovich , Christopher L. Houghton , Stephen C. Root , James J. St. Laurent
IPC分类号： G01R27/02 , G01R27/08 , G01R27/20 , G01R31/30 , G06F11/24 , G01R27/28 , G01R23/16
CPC分类号： G06F11/24 , G01R27/205 , G01R31/3004 , G01R31/3008
摘要： A method comprises generating first and second current levels and measuring the first and second current levels. The method further comprises alternately generating the first and second current levels repeatedly to generate a periodic current waveform, and measuring the voltage at at least one port in a system a plurality of times to obtain a plurality of sets of voltage measurements. The plurality of sets of voltage measurements are averaged. The method further comprises alternately generating the first and second current levels repeatedly at a predetermined number of different clock frequencies, determining a Fourier component of the averaged voltage measurements to determine clock frequency-dependent noises, removing the clock frequency-dependent noises to generate a filtered average voltage, and determining an impedance by dividing a Fourier component of the filtered average voltage by a Fourier component of the periodic current waveform having alternating first and second current levels.
摘要翻译：一种方法包括产生第一和第二电流电平并测量第一和第二电流电平。该方法还包括重复地交替地产生第一和第二电流电平以产生周期性电流波形，并且多次测量系统中至少一个端口处的电压以获得多组电压测量值。对多组电压测量进行平均。该方法还包括以预定数量的不同时钟频率重复地交替产生第一和第二电流电平，确定平均电压测量的傅立叶分量以确定时钟频率相关噪声，去除时钟频率相关噪声以产生滤波平均电压，并且通过将滤波的平均电压的傅立叶分量除以具有交替的第一和第二电流水平的周期性电流波形的傅立叶分量来确定阻抗。

5. 发明授权

US6119075A Method for estimating statistics of properties of interactions processed by a processor pipeline 失效
标题翻译：用于估计由处理器管线处理的交互的属性的统计的方法
公开(公告)号：US6119075A
公开(公告)日：2000-09-12
申请号：US980164
申请日：1997-11-26
申请人： Jeffrey Dean , James E. Hicks , Stephen C. Root , Carl A. Waldspurger , William E. Weihl
发明人： Jeffrey Dean , James E. Hicks , Stephen C. Root , Carl A. Waldspurger , William E. Weihl
IPC分类号： G06F9/38 , G06F11/34 , G06F9/00
CPC分类号： G06F11/3447 , G06F11/3466 , G06F2201/87 , G06F2201/88
摘要： Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A set of instructions are randomly selected from the fetched instructions, a subset of the set of selected instructions concurrently executing with each other. A distances between the set of selected instructions is specified, and state information of the computer system is recorded while the set of selected instructions is being processed by the pipeline. The recorded state information is communicated to software where it is statistically analyzed for a plurality of sets of selected instructions to estimate statistics of the interactions among sets of selected instructions.
摘要翻译：提供了一种用于估计在计算机系统的管线中处理的指令之间的交互的属性的统计的方法，该管线具有多个处理阶段。指令被提取到管道的第一阶段。从所提取的指令中随机选择一组指令，所选指令集合的子集彼此并行执行。指定所选择的指令集之间的距离，并且当所选指令的集合正在由流水线处理时，记录计算机系统的状态信息。所记录的状态信息被传送到软件，在其中统计分析多组所选择的指令以估计所选指令的集合之间的交互的统计。

6. 发明授权

US5159568A High speed parallel multiplier circuit 失效
标题翻译：高速并联电路
公开(公告)号：US5159568A
公开(公告)日：1992-10-27
申请号：US124926
申请日：1987-11-24
申请人： Matthew J. Adiletta , Stephen C. Root
发明人： Matthew J. Adiletta , Stephen C. Root
IPC分类号： G06F7/53 , G06F7/506 , G06F7/508 , G06F7/52
CPC分类号： G06F7/5318
摘要： The binary multiplier circuit for obtaining a product of a M-bit multiplier and a N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most significant bit position. For every column having three or fewer original summand bits, and having the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most significant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits. The remaining two rows of bits can be input to a carry-propagating adder circuit to output a sum equal to the product.

7. 发明授权

US5802373A Method for providing a pipeline interpreter for a variable length instruction set 失效
标题翻译：提供可变长度指令集的流水线解释器的方法
公开(公告)号：US5802373A
公开(公告)日：1998-09-01
申请号：US592982
申请日：1996-01-29
申请人： John S. Yates , Stephen C. Root
发明人： John S. Yates , Stephen C. Root
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/45504
摘要： A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a non-native image of an application program written for a non-native instruction set provides an native instruction or a native instruction routine. The run-time system collects profile data in response to execution of the native instructions to determine execution characteristics of the non-native instruction. Thereafter, the non-native instructions and the profile statistics are fed to a binary translator operating in a background mode and which is responsive to the profile data generated by the run-time system to form a translated native image. The run-time system and the binary translator are under the control of a server process. The non-native image is executed in two different enviroments with first portion executed as an interpreted image and remaining portions as a translated image. The run-time system includes an interpreter which is capable of handling condition codes corresponding to the non-native architecute. A technique is also provided to jacket calls between the two execution enviroments and to support object based services. Preferred techniques are also provide to determine interprocedural translation units. Further, intermixed translation/optimization techniques are discussed.
摘要翻译：一种用于执行二进制图像转换系统的计算机系统，其将来自第一非本机计算机系统的指令集的指令转换为第二，不同的本地计算机系统，包括运行时系统，其响应于非本地图像为非本地指令集编写的应用程序提供本机指令或本地指令例程。运行时系统响应于本地指令的执行而收集简档数据，以确定非本地指令的执行特性。此后，非本地指令和简档统计信息被馈送到在后台模式下操作的二进制翻译器，并且响应于由运行时系统生成的简档数据以形成翻译的本机图像。运行时系统和二进制翻译器都在服务器进程的控制之下。非原始图像在两个不同的环境中执行，第一部分被执行作为解释图像，剩余部分作为翻译图像。运行时系统包括能够处理与非本机结构对应的条件代码的解释器。还提供了一种技术，用于在两个执行环境之间夹紧呼叫并支持基于对象的服务。还提供优选的技术来确定过程间平移单位。此外，讨论了混合翻译/优化技术。

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