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1. 发明授权

US07904494B2 Random number generator with random sampling 失效
标题翻译：随机数发生器随机抽样
公开(公告)号：US07904494B2
公开(公告)日：2011-03-08
申请号：US11608264
申请日：2006-12-08
申请人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
发明人： Choongyeun Cho , Dae Ik Kim , Jonghae Kim , Moon J. Kim
IPC分类号： G06F1/02
CPC分类号： G06F7/588
摘要： In a random number generator, a first converter converts a first analog noise signal into a random digital clock signal and a second converter samples a second analog noise signal asynchronous to the first analog noise signal in response to the random digital clock signal and generates a random digital number stream. In one aspect, a random number generator output block samples the second converter random digital number stream in response to the random digital clock signal and generates a random number generator block output. In another aspect a pseudo noise source state machine generates the random digital clock signal in response to a first seed generated from the first analog noise signal, a second seed from process variation digital amplifier, and a past machine state.
摘要翻译：在随机数发生器中，第一转换器将第一模拟噪声信号转换为随机数字时钟信号，并且第二转换器响应于随机数字时钟信号对与第一模拟噪声信号异步的第二模拟噪声信号进行采样，并产生随机数数字数字流。一方面，随机数发生器输出块响应于随机数字时钟信号对第二转换器随机数字数字流进行采样，并产生随机数发生器块输出。在另一方面，伪噪声源状态机响应于从第一模拟噪声信号产生的第一种子，来自过程变化数字放大器的第二种子和过去的机器状态，产生随机数字时钟信号。

2. 发明授权

US07902880B2 Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer 有权
标题翻译：通过背栅电荷转移将数字集成电路从待机模式转换到主动模式
公开(公告)号：US07902880B2
公开(公告)日：2011-03-08
申请号：US12844339
申请日：2010-07-27
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
IPC分类号： H01L25/00 , H03K19/00
CPC分类号： H03K19/0016 , Y10T29/49002
摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
摘要翻译：提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管基板和背栅控制电路。背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

3. 发明申请

US20100066496A1 ACOUSTIC WAVE AND RADIO FREQUENCY IDENTIFICATION DEVICE AND METHOD 失效
标题翻译：声波和无线电频率识别装置及方法
公开(公告)号：US20100066496A1
公开(公告)日：2010-03-18
申请号：US12210371
申请日：2008-09-15
申请人： Choongyeun CHO , Richard FERRI , Daeik KIM , Jonghae KIM , Moon Ju KIM
发明人： Choongyeun CHO , Richard FERRI , Daeik KIM , Jonghae KIM , Moon Ju KIM
IPC分类号： H04Q5/22
CPC分类号： H04Q9/00 , H04Q2209/47
摘要： An identification method and identification device are presented employing radio frequency and acoustic wave communication modes. The identification method includes: receiving at an acoustic wave and radio frequency identification device an acoustic wave signal of a first frequency and a radio frequency signal of a second frequency, where the acoustic wave signal and the radio frequency signal are received from an acoustic wave and radio frequency identification reader, and the first frequency and the second frequency are different frequencies; and responding to the receiving by transmitting at least one of an acoustic wave identification (AWID) or a radio frequency identification (RFID) from the acoustic wave and radio frequency identification device.
摘要翻译：采用射频和声波通信方式提出了识别方法和识别装置。识别方法包括：在声波和射频识别装置处接收第一频率的声波信号和从声波接收声波信号和射频信号的第二频率的射频信号，射频识别读取器，第一频率和第二频率是不同的频率; 以及通过从声波和射频识别装置发送声波识别（AWID）或射频识别（RFID）中的至少一个来响应于接收。

4. 发明申请

US20070267733A1 Symmetrical MIMCAP capacitor design 审中-公开
标题翻译：对称MIMCAP电容设计
公开(公告)号：US20070267733A1
公开(公告)日：2007-11-22
申请号：US11436251
申请日：2006-05-18
申请人： Choongyeun Cho , Jonghae Kim , Moon Kim , Jean-Olivier Plouchart , Robert Trzcinski
发明人： Choongyeun Cho , Jonghae Kim , Moon Kim , Jean-Olivier Plouchart , Robert Trzcinski
IPC分类号： H01L23/06
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor chip capacitance circuits and methods are provided comprising at least two capacitors mounted close to a substrate, wherein each capacitor has a lateral lower conductive plate mounted near enough to the substrate to have extrinsic capacitance greater than an upper plate extrinsic capacitance. One half of lower plates and one half of upper plates are connected to a first port, and a remaining one half of upper plates and lower plates are connected to a second port, the first and second port having about equal extrinsic capacitance from the lower plates. In one aspect, the substrate comprises a front-end-of-line capacitor defining a substrate footprint, and the at least two capacitors are back-end-of-line Metal-Insulator-Metal Capacitors disposed above the footprint. In another aspect, the at least two capacitors are at least four capacitors arrayed in a rectangular array generally parallel to the substrate.
摘要翻译：提供半导体芯片电容电路和方法，其包括安装在基板附近的至少两个电容器，其中每个电容器具有安装在基板附近的侧向下导电板，以具有大于上板外部电容的非本征电容。下板的一半和上板的一半连接到第一端口，并且上板和下板的剩余的一半连接到第二端口，第一和第二端口具有与下板大致相等的外在电容。在一个方面，衬底包括限定衬底占位面积的前端电容器，并且至少两个电容器是设置在覆盖区之上的后端金属 - 绝缘体 - 金属电容器。在另一方面，所述至少两个电容器是至少四个电容器，其排列成大致平行于衬底的矩形阵列。

5. 发明授权

US08273648B2 Circuit structures and methods with BEOL layers configured to block electromagnetic edge interference 有权
公开(公告)号：US08273648B2
公开(公告)日：2012-09-25
申请号：US13369592
申请日：2012-02-09
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim , James R. Moulic
IPC分类号： H01L21/3205
CPC分类号： H01L23/5225 , H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back-end-of-line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic edge interference. One such BEOL circuit structure includes a semiconductor substrate supporting one or more integrated circuits, and multiple BEOL layers disposed over the semiconductor substrate. The multiple BEOL layers extend to an edge of the circuit structure and include at least one vertically-extending conductive pattern disposed adjacent to the edge of the circuit structure. The vertically-extending conductive pattern is defined, at least partially, by a plurality of elements disposed in the multiple BEOL layers. The plurality of elements are uniformly arrayed at the edge of the circuit structure in a first direction or a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in the first direction or the second direction to block electromagnetic interference of a particular wavelength from passing therethrough.

6. 发明授权

US07821110B2 Circuit structures and methods with BEOL layer(s) configured to block electromagnetic interference 有权
标题翻译： BEOL层的电路结构和方法被配置为阻止电磁干扰
公开(公告)号：US07821110B2
公开(公告)日：2010-10-26
申请号：US11747342
申请日：2007-05-11
申请人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
发明人： Dae Ik Kim , Jonghae Kim , Moon Ju Kim , Choongyeun Cho
IPC分类号： H01L23/552
CPC分类号： H01L23/552 , H01L2924/0002 , H01L2924/00
摘要： Back end of line (BEOL) circuit structures and methods are provided for blocking externally-originating or internally-originating electromagnetic interference. One such BEOL circuit structure includes one or more semiconductor substrates supporting one or more integrated circuits, and one or more BEOL layers disposed over the semiconductor substrate(s). At least one BEOL layer includes a conductive pattern defined at least partially by a plurality of elements arrayed in a first direction and a second direction throughout at least a portion thereof. The plurality of elements are sized and positioned in at least one of the first and second directions to block electromagnetic interference of a particular wavelength from passing therethrough. In one implementation, a first conductive pattern of a first BEOL layer polarizes electromagnetic interference, and a second conductive pattern of a second BEOL layer blocks the polarized electromagnetic interference.
摘要翻译：提供后端（BEOL）电路结构和方法来阻止外部来源或内部产生的电磁干扰。一种这样的BEOL电路结构包括支撑一个或多个集成电路的一个或多个半导体衬底以及设置在半导体衬底之上的一个或多个BEOL层。至少一个BEOL层包括至少部分地由在第一方向和第二方向排列的多个元件至少部分地限定的导电图案。多个元件的大小和位置在第一和第二方向中的至少一个方向上，以阻止特定波长的电磁干扰通过。在一个实施方案中，第一BEOL层的第一导电图案使电磁干扰偏振，并且第二BEOL层的第二导电图案阻挡极化的电磁干扰。

7. 发明授权

US07791403B2 Transitioning digital integrated circuit from standby mode to active mode via backgate charge transfer 失效
标题翻译：通过背栅电荷转移将数字集成电路从待机模式转换到主动模式
公开(公告)号：US07791403B2
公开(公告)日：2010-09-07
申请号：US12206124
申请日：2008-09-08
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon Ju Kim
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H03K19/0016 , Y10T29/49002
摘要： Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.
摘要翻译：提供了电路和方法，以便于将数字电路从背栅极偏置待机模式转换到主动模式。数字电路包括半导体衬底，至少部分地设置在半导体衬底中的一个或多个p型阱中的多个n沟道晶体管，至少部分地设置在半导体中的一个或多个n型阱中的多个p沟道晶体管基板和背栅控制电路。背栅控制电路电耦合到p型阱和n型阱，以便于将多个n沟道晶体管和多个p沟道晶体管从背栅极偏置待机模式转换到有源模式，通过自动将电荷从n型阱转移到p型阱，直到达到阱电压阈值，表明晶体管从背栅极偏置待机模式到活动模式的完成转变。

8. 发明授权

US07504705B2 Striped on-chip inductor 失效
标题翻译：条形片上电感
公开(公告)号：US07504705B2
公开(公告)日：2009-03-17
申请号：US11536896
申请日：2006-09-29
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： G06F17/50
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

9. 发明申请

US20120223411A1 STRIPED ON-CHIP INDUCTOR 有权
标题翻译：带状片上电感器
公开(公告)号：US20120223411A1
公开(公告)日：2012-09-06
申请号：US13469464
申请日：2012-05-11
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , Jean-Olivier Plouchart , Robert E. Trzcinski
IPC分类号： H01L29/86 , H01L21/02
CPC分类号： H01L28/10 , H01F17/0013 , H01F2017/0073 , H01L23/5227 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Sub-100 nanometer semiconductor devices and methods and program products for manufacturing devices are provided, in particular inductors comprising a plurality of spaced parallel metal lines disposed on a dielectric surface and each having width, heights, spacing and cross-sectional areas determined as a function of Design Rule Check rules. For one planarization process rule a metal density ratio of 80% metal to 20% dielectric surface is determined and produced. In one example a sum of metal line spacing gaps is less than a sum of metal line interior sidewall heights. In one aspect at least one of line height, width and line spacing dimensions is selected to optimize one or more chip yield, chip performance, chip manufacturability and inductor Q factor parameters.
摘要翻译：提供了用于制造器件的亚100纳米半导体器件和方法和程序产品，特别是电感器，其包括设置在电介质表面上的多个间隔开的平行金属线，并且每个具有确定为功能的宽度，高度，间隔和横截面面积的设计规则检查规则。对于一个平面化工艺规则，确定并生产了80％金属至20％电介质表面的金属密度比。在一个示例中，金属线间距的总和小于金属线内侧壁高度的总和。在一个方面，选择线高度，宽度和线间距尺寸中的至少一个以优化一个或多个芯片产量，芯片性能，芯片制造性和电感器Q因子参数。

10. 发明申请

US20120194792A1 METHOD AND SYSTEM TO PREDICT LITHOGRAPHY FOCUS ERROR USING SIMULATED OR MEASURED TOPOGRAPHY 有权
标题翻译：使用模拟或测量的地形来预测地震聚焦误差的方法和系统
公开(公告)号：US20120194792A1
公开(公告)日：2012-08-02
申请号：US13014803
申请日：2011-01-27
申请人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
发明人： Brian Christopher Sapp , Choongyeun Cho , Lawrence A. Clevenger , Laertis Economikos , Bernhard R. Liegl , Kevin S. Petrarca , Roger Allan Quon
IPC分类号： G03B27/52
CPC分类号： G03F7/7065 , G03F7/70066 , G03F7/705 , G03F7/70525 , G03F7/70641 , G03F9/7026 , G06F17/5009 , G06F17/5081
摘要： A method and system to predict lithography focus error using chip topography data is disclosed. The chip topography data may be measured or simulated topography data. A plane is best fitted to the topography data, and residuals are computed. The residuals are then used to make a prediction regarding the focus error. The density ratio of metal to dielectric may also be used as a factor in determining the predicted focus error.
摘要翻译：公开了使用芯片形貌数据来预测光刻聚焦误差的方法和系统。可以测量或模拟地形数据的芯片地形数据。平面最适合地形数据，并计算残差。然后，残差用于对聚焦误差进行预测。金属与电介质的密度比也可用作确定预测的聚焦误差的因素。

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