专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080079090A1 Semiconductor device including recessed spherical silicide contact part and method of manufacturing the same 审中-公开
标题翻译：包括凹形球形硅化物接触部件的半导体器件及其制造方法
公开(公告)号：US20080079090A1
公开(公告)日：2008-04-03
申请号：US11900772
申请日：2007-09-13
申请人： Hong-kyu Hwang , Dae-ik Kim , Seung-beom Kim
发明人： Hong-kyu Hwang , Dae-ik Kim , Seung-beom Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/76804 , H01L21/76834 , H01L21/76889 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and fabrication method thereof protect an overgrown metal silicide layer from external damage. The semiconductor device includes: isolation regions formed on a substrate; source/drain regions in the substrate between the isolation regions; a first interlayer insulating film on the substrate, the isolation regions and the source/drain regions; contact pads vertically penetrating the first interlayer insulating film and electrically connected to the source/drain regions; a second interlayer insulating film on the first interlayer insulating film and the contact pads; a metal silicide region selectively formed on the contact pads at a vertical position that is lower than an upper surface of the first interlayer insulating film; and a contact plug vertically penetrating the second interlayer insulating film and electrically connected to the metal silicide region.
摘要翻译：一种半导体器件及其制造方法，其保护过度生长的金属硅化物层免受外部损坏。半导体器件包括：形成在衬底上的隔离区; 在隔离区之间的衬底中的源/漏区; 衬底上的第一层间绝缘膜，隔离区和源极/漏极区; 垂直穿过第一层间绝缘膜并电连接到源极/漏极区的接触焊盘; 在第一层间绝缘膜和接触焊盘上的第二层间绝缘膜; 选择性地形成在所述接触焊盘上的垂直位置处的金属硅化物区域，所述垂直位置比所述第一层间绝缘膜的上表面低; 以及垂直贯穿第二层间绝缘膜并与金属硅化物区电连接的接触插塞。

2. 发明授权

US06548388B2 Semiconductor device including gate electrode having damascene structure and method of fabricating the same 失效
公开(公告)号：US06548388B2
公开(公告)日：2003-04-15
申请号：US09805213
申请日：2001-03-14
申请人： Hong-kyu Hwang , Young-Rae Park , Jung-yup Kim , Jeong-sic Jeon , Bo-un Yoon , Sang-rok Hah
发明人： Hong-kyu Hwang , Young-Rae Park , Jung-yup Kim , Jeong-sic Jeon , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L213205
CPC分类号： H01L21/76897 , H01L21/28123 , H01L21/76832 , H01L21/76834 , H01L21/76837 , H01L21/823437 , H01L21/823481
摘要： A gate electrode conductive layer is formed on an active region that is recessed relative to field oxide layers so as to define a damascene structure. The gate electrode conductive layer is formed on the active region but is not formed on a field region so that the thickness of an interlayer insulation layer deposited in a succeeding process is reduced, thereby reducing or preventing voids within the interlayer insulation layer. A polysilicon is formed on the bottom of the active region by selective epitaxial growth, thereby minimizing the influence of micro scratches, pits or stringers occurring on the bottom of the active region.

3. 发明授权

US06335287B1 Method of forming trench isolation regions 有权
标题翻译：形成沟槽隔离区域的方法
公开(公告)号：US06335287B1
公开(公告)日：2002-01-01
申请号：US09637788
申请日：2000-08-11
申请人： Hong-kyu Hwang , Bo-un Yoon , Kyu-hwan Chang , Sang-rok Hah
发明人： Hong-kyu Hwang , Bo-un Yoon , Kyu-hwan Chang , Sang-rok Hah
IPC分类号： H01L12302
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31055
摘要： To form isolation trenches on a semiconductor substrate, chemical mechanical polishing (CMP) stopping patterns are formed on the substrate, and the substrate is then etched using the CMP stopping patterns as a mask. Then an insulating material is deposited to fill the trenches and cover the CMP stopping patterns. The insulating material is etched using a CMP process until the CMP stopping patterns become exposed, and is then etched using a wet or dry etching process. The wet or dry etching is continued until protruding insulating material above a surface of the substrate is a predetermined thickness, which corresponds to an amount of the insulating material that is etched during removal of the CMP stopping patterns and during intermediate processes prior to formation of a gate oxide layer.
摘要翻译：为了在半导体衬底上形成隔离沟槽，在衬底上形成化学机械抛光（CMP）停止图案，然后使用CMP停止图案作为掩模蚀刻衬底。然后沉积绝缘材料以填充沟槽并覆盖CMP停止图案。使用CMP工艺蚀刻绝缘材料，直到CMP停止图案露出，然后使用湿法或干蚀刻工艺进行蚀刻。继续进行湿法或干蚀刻蚀刻，直到基片表面上方的突出的绝缘材料为预定的厚度，这对应于在去除CMP停止图案期间以及在形成CMP停止图案之间的中间工艺期间被蚀刻的绝缘材料的量栅氧化层。

4. 发明授权

US06695684B2 Chemical mechanical polishing apparatus having a cleaner for cleaning a conditioning disc and method of conditioning a polishing pad of the apparatus 失效
标题翻译：具有用于清洁调节盘的清洁剂的化学机械抛光装置和调节该装置的抛光垫的方法
公开(公告)号：US06695684B2
公开(公告)日：2004-02-24
申请号：US09969992
申请日：2001-10-04
申请人： Young-rae Park , Ho-young Kim , Hong-kyu Hwang
发明人： Young-rae Park , Ho-young Kim , Hong-kyu Hwang
IPC分类号： B24B100
CPC分类号： B24B53/017 , H01L21/67046
摘要： A chemical mechanical polishing apparatus includes a polishing pad on which a wafer requiring planarization is placed, a conditioning disc having an abrasive surface for conditioning the polishing pad, a tank containing de-ionized water in which the conditioning disc soaks while standing by, and a cleaner for cleaning the conditioning disc. The conditioning disc cleaner is disposed in the tank of de-ionized water to remove polishing impurities from an abrasive surface of the conditioning disc. The cleaner may include a brush having bristles against which the abrasive surface of the conditioning disc is placed when it is lowered into the tank. In operation, after the wafer is polished, an abrasive surface of the conditioning disc is run over the upper surface of the polishing pad to condition the surface of the polishing pad. Then the conditioning disc is moved off of the upper surface of the polishing pad and to a stand-by position in which the abrasive surface of the disc is submerged in a liquid. Finally, while the conditioning disc is in its stand-by position, impurities are forced off of the abrasive surface and into the liquid by the cleaner disposed in the liquid. The conditioning disc is thus cleaned so that impurities are not transferred to the polishing pad during the next conditioning process.
摘要翻译：化学机械抛光装置包括其上放置有需要平面化的晶片的抛光垫，具有用于调节抛光垫的研磨表面的调节盘，包含调节盘在静置时浸泡的去离子水的罐，以及用于清洁调理盘的清洁剂。调节盘清洁器设置在去离子水的罐中，以从调理盘的研磨表面去除抛光杂质。清洁器可以包括具有刷毛的刷子，当调节盘的研磨表面下降到罐中时，该刷头与该刷头对准。在操作中，在抛光晶片之后，调节盘的研磨表面在抛光垫的上表面上延伸以调节抛光垫的表面。然后调节盘从抛光垫的上表面移动到盘的研磨表面浸没在液体中的待机位置。最后，当调节盘处于其待机位置时，通过设置在液体中的清洁剂将杂质从研磨表面强制离开液体。因此，调节盘被清洁，使得杂质在下一个调理过程中不会转移到抛光垫。

5. 发明授权

US06518157B2 Methods of planarizing insulating layers on regions having different etching rates 失效
公开(公告)号：US06518157B2
公开(公告)日：2003-02-11
申请号：US09917601
申请日：2001-07-27
申请人： Gee-won Nam , Gi-jong Park , Hong-kyu Hwang , Jun-shik Bae , Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
发明人： Gee-won Nam , Gi-jong Park , Hong-kyu Hwang , Jun-shik Bae , Young-rae Park , Jung-yup Kim , Bo-un Yoon , Sang-rok Hah
IPC分类号： H01L2144
CPC分类号： H01L21/31056 , H01L21/31053 , H01L21/76819
摘要： An insulating layer can be formed on first and second adjacent regions of an integrated circuit having a first step difference therebetween, the first and second regions having first and second respective etch rates associated therewith. A recess can be formed in the insulating layer on the second region having a second step difference with the first region that is less than the first step difference to provide a portion of the insulating layer between the first and second adjacent regions having a third step difference with the first region that is greater than the second step difference. A width of the portion is selected based on a difference between the first and second etch rates.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式