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1. 发明授权

US5654231A Method of eliminating buried contact trench in SRAM technology 失效
标题翻译：在SRAM技术中消除埋接触沟的方法
公开(公告)号：US5654231A
公开(公告)日：1997-08-05
申请号：US621273
申请日：1996-03-25
申请人： Mong-Song Liang , Jin-Yuan Lee , Chun-Yi Shih
发明人： Mong-Song Liang , Jin-Yuan Lee , Chun-Yi Shih
IPC分类号： H01L21/28 , H01L21/8244
CPC分类号： H01L27/11 , H01L21/28
摘要： A new method of forming an improved buried contact junction is described. A first polysilicon layer is deposited overlying a gate silicon oxide layer on the surface of a semiconductor substrate. The first polysilicon and gate oxide layers are etched away where they are not covered by a buried contact mask to provide an opening to the semiconductor substrate. Ions are implanted through the opening into the semiconductor substrate to form a buried contact junction. A layer of dielectric material is deposited over the first polysilicon layer and over the semiconductor substrate within the opening. The layer is anisotropically etched to leave spacers on the sidewalls of the first polysilicon layer and adjacent the opening. A second layer of polysilicon is deposited overlying the first polysilicon layer and over the substrate within the opening. The second polysilicon layer is patterned to form gate electrodes and a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and a portion of a spacer overlying the buried contact junction is exposed and wherein a portion of the second polysilicon layer other than that of the contact remains as residue. The second polysilicon layer residue is etched away wherein the exposed spacer protects the buried contact junction within the semiconductor substrate from the etching to complete the formation of a buried contact in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。沉积在半导体衬底的表面上的栅极氧化硅层上的第一多晶硅层。第一多晶硅和栅极氧化物层被蚀刻掉，其中它们不被掩埋的接触掩模覆盖以提供到半导体衬底的开口。离子通过开口植入半导体衬底中以形成掩埋接触结。电介质材料层沉积在开口内的第一多晶硅层上方和半导体衬底之上。该层被各向异性地蚀刻以在第一多晶硅层的侧壁和邻近开口处留下间隔物。第二层多晶硅沉积在第一多晶硅层的上方并且在开口内的衬底上。图案化第二多晶硅层以形成栅电极和覆盖掩埋接触结的多晶硅接触，其中用于图案化的掩模不对准，并且覆盖掩埋接触结的间隔物的一部分被暴露，并且其中第二多晶硅层的一部分除了接触物以外，残留物残留。第二多晶硅层残留物被蚀刻掉，其中暴露的间隔物保护半导体衬底内的掩埋接触结点免受蚀刻，以在集成电路的制造中完成掩埋接触的形成。

2. 发明授权

US5554558A Method of making high precision w-polycide-to-poly capacitors in digital/analog process 失效
标题翻译：在数字/模拟过程中制造高精度w-polycide-to-poly电容器的方法
公开(公告)号：US5554558A
公开(公告)日：1996-09-10
申请号：US387081
申请日：1995-02-13
申请人： Shun-Liang Hsu , Jyh-Kang Ting , Chun-Yi Shih
发明人： Shun-Liang Hsu , Jyh-Kang Ting , Chun-Yi Shih
IPC分类号： H01L21/02 , H01L21/3105 , H01L27/06 , H01L21/70 , H01L27/00
CPC分类号： H01L28/40 , H01L21/3105 , H01L27/0629
摘要： A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.
摘要翻译：描述了具有降低的IPO厚度和低电压系数的制造多晶硅对多晶硅电容器的方法。在硅衬底上形成第一掺杂多晶硅层。在第一掺杂多晶硅层上形成硅化物层。将第一层掺杂多晶硅和硅化物层图案化以形成电容器的多晶硅底板。在底板上形成氧化物层。氧化层被致密化。第二层掺杂多晶硅形成在氧化物层上。图案化第二层多晶硅以形成电容器的顶板。去除氧化层，除了在电容器的顶板之下，其中它用作电容器电介质，最后，底板被退火。

3. 发明授权

US5804488A Method of forming a tungsten silicide capacitor having a high breakdown voltage 失效
标题翻译：形成具有高击穿电压的硅化钨电容器的方法
公开(公告)号：US5804488A
公开(公告)日：1998-09-08
申请号：US518702
申请日：1995-08-24
申请人： Chun-Yi Shih , Shun-Liang Hsu , Jyh-Kang Ting
发明人： Chun-Yi Shih , Shun-Liang Hsu , Jyh-Kang Ting
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/60
摘要： A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.
摘要翻译：描述了制造具有改进的击穿电压的多晶硅 - 多晶硅电容器的方法。在硅衬底上形成第一掺杂多晶硅层。在第一掺杂多晶硅层上形成硅化物层。在硅化物层上形成氧化物层，然后将硅化物层退火。第二层掺杂多晶硅形成在氧化物层上。图案化第二层掺杂多晶硅以形成电容器的顶板。去除氧化物层，除了在电容器的顶板之下，其作为电容器电介质。将第一层掺杂多晶硅和硅化物层图案化以形成电容器的多晶硅底板。

4. 发明授权

US5846860A Method of making buried contact in DRAM technology 失效
标题翻译：在DRAM技术中进行埋地接触的方法
公开(公告)号：US5846860A
公开(公告)日：1998-12-08
申请号：US668801
申请日：1996-06-24
申请人： Chun-Yi Shih , Julie Huang , Mong-Song Liang
发明人： Chun-Yi Shih , Julie Huang , Mong-Song Liang
IPC分类号： H01L21/285 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/28537 , Y10S148/02
摘要： A new method of forming an improved buried contact junction is described. Word lines are provided over the surface of a semiconductor substrate. A first insulating layer is deposited overlying the word lines. The first insulating layer is etched away where it is not covered by a buried contact mask to provide an opening to the semiconductor substrate. A layer of tetraethoxysilane (TEOS) silicon oxide is deposited over the first insulating layer and over the semiconductor substrate within the opening. The TEOS layer is anisotropically etched to leave spacers on the sidewalls of the word lines and of the first insulating layer. A first layer of polysilicon is deposited overlying the first insulating layer and within the opening. The first polysilicon layer is doped with dopant which is driven in to form a buried contact junction within the semiconductor substrate under the opening. The first polysilicon layer is patterned to form a polysilicon contact overlying the buried contact junction wherein the mask used for the patterning is misaligned and wherein a portion of a TEOS spacer overlying the buried contact junction is exposed and wherein a portion of the first polysilicon layer other than that of the contact remains as residue. The first polysilicon layer residue is etched away wherein the exposed TEOS spacer protects the buried contact junction within the semiconductor substrate from the etching completing the formation of a buried contact in the fabrication of an integrated circuit.
摘要翻译：描述了形成改进的埋地接触结的新方法。字线设置在半导体衬底的表面上。第一绝缘层沉积在字线上方。第一绝缘层被蚀刻掉，其中它不被掩埋的接触掩模覆盖以提供到半导体衬底的开口。一层四乙氧基硅烷（TEOS）氧化硅沉积在第一绝缘层上方，并在该开口内的半导体衬底上。 TEOS层被各向异性地蚀刻以将间隔物留在字线和第一绝缘层的侧壁上。第一层多晶硅沉积在第一绝缘层上并且在开口内。第一多晶硅层掺杂掺杂剂，掺杂剂被驱动以在开口下的半导体衬底内形成掩埋接触结。第一多晶硅层被图案化以形成覆盖掩埋接触结的多晶硅接触，其中用于图案化的掩模未对准，并且其中覆盖掩埋接触结的TEOS间隔物的一部分被暴露，并且其中第一多晶硅层的一部分其他比接触物残留物残留。蚀刻掉第一多晶硅层残留物，其中暴露的TEOS间隔物保护半导体衬底内的掩埋接触结合层免于在集成电路的制造中完成掩埋接触的形成。

5. 发明授权

US5451529A Method of making a real time ion implantation metal silicide monitor 失效
标题翻译：制造实时离子注入金属硅化物监测器的方法
公开(公告)号：US5451529A
公开(公告)日：1995-09-19
申请号：US270764
申请日：1994-07-05
申请人： Shun-Liang Hsu , Chun-Yi Shih
发明人： Shun-Liang Hsu , Chun-Yi Shih
IPC分类号： H01L21/66 , H01L23/544 , H01L21/00
CPC分类号： H01L22/26 , H01L22/34 , Y10S148/083 , Y10S148/162
摘要： A novel technique for the real time monitoring of ion implant doses has been invented. This is the first real-time monitor to cover the high dosage range (10E13 to 10E16 ions/sq. cm.). The underlying principle of this new technique is the increase in the resistance of a metal silicide film after ion implantation. Measurement of this increase in a silicide film that has been included in a standard production wafer provides an index for correlation with the implanted ion dose.
摘要翻译：已经发明了用于实时监测离子注入剂量的新技术。这是第一个覆盖高剂量范围（10E13至10E16离子/平方厘米）的实时显示器。这种新技术的基本原理是离子注入后金属硅化物膜的电阻增加。已经包括在标准生产晶片中的硅化物膜的这种增加的测量提供了与植入离子剂量相关的指标。

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