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1. 发明授权

US5554558A Method of making high precision w-polycide-to-poly capacitors in digital/analog process 失效
标题翻译：在数字/模拟过程中制造高精度w-polycide-to-poly电容器的方法
公开(公告)号：US5554558A
公开(公告)日：1996-09-10
申请号：US387081
申请日：1995-02-13
申请人： Shun-Liang Hsu , Jyh-Kang Ting , Chun-Yi Shih
发明人： Shun-Liang Hsu , Jyh-Kang Ting , Chun-Yi Shih
IPC分类号： H01L21/02 , H01L21/3105 , H01L27/06 , H01L21/70 , H01L27/00
CPC分类号： H01L28/40 , H01L21/3105 , H01L27/0629
摘要： A method for making a polycide-to-polysilicon capacitor, which has a reduced IPO thickness and low voltage coefficient, is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor. An oxide layer is formed over the bottom plate. The oxide layer is densified. A second layer of doped polysilicon is formed over the oxide layer. The second layer of polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric, and, finally, the bottom plate is annealed.
摘要翻译：描述了具有降低的IPO厚度和低电压系数的制造多晶硅对多晶硅电容器的方法。在硅衬底上形成第一掺杂多晶硅层。在第一掺杂多晶硅层上形成硅化物层。将第一层掺杂多晶硅和硅化物层图案化以形成电容器的多晶硅底板。在底板上形成氧化物层。氧化层被致密化。第二层掺杂多晶硅形成在氧化物层上。图案化第二层多晶硅以形成电容器的顶板。去除氧化层，除了在电容器的顶板之下，其中它用作电容器电介质，最后，底板被退火。

2. 发明授权

US5804488A Method of forming a tungsten silicide capacitor having a high breakdown voltage 失效
标题翻译：形成具有高击穿电压的硅化钨电容器的方法
公开(公告)号：US5804488A
公开(公告)日：1998-09-08
申请号：US518702
申请日：1995-08-24
申请人： Chun-Yi Shih , Shun-Liang Hsu , Jyh-Kang Ting
发明人： Chun-Yi Shih , Shun-Liang Hsu , Jyh-Kang Ting
IPC分类号： H01L21/02 , H01L21/20 , H01L21/8242
CPC分类号： H01L28/60
摘要： A method for making a polycide-to-polysilicon capacitor having an improved breakdown voltage is described. A first layer of doped polysilicon is formed over a silicon substrate. A silicide layer is formed over the first layer of doped polysilicon. An oxide layer is formed over the silicide layer, and the silicide layer is then annealed. A second layer of doped polysilicon is formed over the oxide layer. The second layer of doped polysilicon is patterned to form a top plate of the capacitor. The oxide layer is removed except under the top plate of the capacitor, where it acts as a capacitor dielectric. The first layer of doped polysilicon and the silicide layer are patterned to form a polycide bottom plate of the capacitor.
摘要翻译：描述了制造具有改进的击穿电压的多晶硅 - 多晶硅电容器的方法。在硅衬底上形成第一掺杂多晶硅层。在第一掺杂多晶硅层上形成硅化物层。在硅化物层上形成氧化物层，然后将硅化物层退火。第二层掺杂多晶硅形成在氧化物层上。图案化第二层掺杂多晶硅以形成电容器的顶板。去除氧化物层，除了在电容器的顶板之下，其作为电容器电介质。将第一层掺杂多晶硅和硅化物层图案化以形成电容器的多晶硅底板。

3. 发明授权

US5480828A Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process 失效
标题翻译：通过抑制或提高混合3/5 V CMOS工艺的氧化速率的差分栅极氧化工艺
公开(公告)号：US5480828A
公开(公告)日：1996-01-02
申请号：US316084
申请日：1994-09-30
申请人： Shun-Liang Hsu , Jyh-Min Tsaur , Mou S. Lin , Jyh-Kang Ting
发明人： Shun-Liang Hsu , Jyh-Min Tsaur , Mou S. Lin , Jyh-Kang Ting
IPC分类号： H01L21/8234
CPC分类号： H01L21/823462 , Y10S148/116 , Y10S438/981
摘要： A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate. The growth rate of the gate silicon oxide will be slowed in the planned 3 V transistor area or will be increased in the planned 5 V transistor area resulting in a gate silicon oxide layer which is relatively thinner in the planned 3 V transistor area and relatively thicker in the planned 5 V transistor area. A layer of polysilicon is deposited over the gate silicon oxide layer and patterned to form gate electrodes for the 3V and 5V transistors.
摘要翻译：描述了同时形成3和5 V晶体管的差分栅极氧化物的新方法。牺牲氧化硅层形成在半导体衬底的表面上。离子通过牺牲氧化硅层注入到半导体衬底的预定的3V晶体管区域中，其中注入的离子降低半导体衬底的氧化速率。或者，离子通过牺牲氧化硅层注入到半导体衬底的预定的5V晶体管区域中，其中注入的离子增加了半导体衬底的氧化速率。去除牺牲氧化硅层，并在半导体衬底的表面上生长栅极氧化硅层。栅极氧化硅的生长速率将在预定的3 V晶体管面积中减慢，或者将在计划的5 V晶体管区域中增加，从而导致栅极氧化硅层在计划的3 V晶体管区域中相对较薄，并且相对较厚在计划的5 V晶体管区域。一层多晶硅沉积在栅极氧化硅层上并被图案化以形成用于3V和5V晶体管的栅电极。

4. 发明授权

US08769475B2 Method, system and software for accessing design rules and library of design features while designing semiconductor device layout 有权
标题翻译：在设计半导体器件布局时，用于访问设计规则和设计特征库的方法，系统和软件
公开(公告)号：US08769475B2
公开(公告)日：2014-07-01
申请号：US13285528
申请日：2011-10-31
申请人： Chin-An Chen , Pei-Tzu Wu , Tsung-Chieh Tsai , Juing-Yi Wu , Jyh-Kang Ting
发明人： Chin-An Chen , Pei-Tzu Wu , Tsung-Chieh Tsai , Juing-Yi Wu , Jyh-Kang Ting
IPC分类号： G06F15/04 , G06F17/50
CPC分类号： G06F17/5081
摘要： Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.
摘要翻译：提供了一种用于设计集成电路或其他半导体器件的布局的系统和方法，同时通过与显示设计布局的GUI对接地直接访问设计规则和设计特征库。设计规则可以直接链接到图案库的设计特征并导入设备布局。设计规则可以在设计布局时进行直接访问，或者在进行设计规则检查时，可以使用图案库中的设计特征来创建布局。

5. 发明申请

US20070158835A1 Method for designing interconnect for a new processing technology 审中-公开
标题翻译：用于设计新加工技术的互连的方法
公开(公告)号：US20070158835A1
公开(公告)日：2007-07-12
申请号：US11332566
申请日：2006-01-12
申请人： Jian-Hong Lin , Hsueh-Chung Chen , Yi-Lung Cheng , Ta-Wei Lee , Chih-Tao Lin , Jyh-Kang Ting , Lee-Chung Lu
发明人： Jian-Hong Lin , Hsueh-Chung Chen , Yi-Lung Cheng , Ta-Wei Lee , Chih-Tao Lin , Jyh-Kang Ting , Lee-Chung Lu
IPC分类号： H01L23/48
CPC分类号： H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for determining a size of an interconnect between a first and a second conductor respectively in two layers of an integrated circuit while scaling from a reference processing technology to a predetermined processing technology. The method comprises selecting a set of design rules for the conductors based on the predetermined processing technology, determining a length of a first side of a rectangular cross sectional area of the interconnect based on the design rules and a scaling rule for scaling such a length from the reference processing technology to the predetermined processing technology, and determining a length of a second side of the cross sectional area of the interconnect for compensating an increase of a resistance of the interconnect due to the scaling from the reference processing technology to the predetermined processing technology.
摘要翻译：公开了一种用于在从参考处理技术缩放到预定处理技术的同时，分别在集成电路的两层中确定第一和第二导体之间的互连尺寸的方法。该方法包括基于预定的处理技术来选择一组导体的设计规则，基于设计规则确定互连的矩形横截面积的第一侧的长度，以及用于缩放这种长度的缩放规则将参考处理技术应用于预定处理技术，以及确定互连横截面积的第二侧的长度，以补偿由于从参考处理技术到预定处理技术的缩放而导致的互连电阻的增加。

6. 发明申请

US20130111418A1 METHOD, SYSTEM AND SOFTWARE FOR ACCESSING DESIGN RULES AND LIBRARY OF DESIGN FEATURES WHILE DESIGNING SEMICONDUCTOR DEVICE LAYOUT 有权
标题翻译：用于访问设计规则的方法，系统和软件以及设计半导体器件布局时的设计特征库
公开(公告)号：US20130111418A1
公开(公告)日：2013-05-02
申请号：US13285528
申请日：2011-10-31
申请人： Chin-An Chen , Pei-Tzu Mu , Tsung-Chieh Tsai , Juing-Yi Wu , Jyh-Kang Ting
发明人： Chin-An Chen , Pei-Tzu Mu , Tsung-Chieh Tsai , Juing-Yi Wu , Jyh-Kang Ting
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： Provided is a system and method for designing the layout of integrated circuits or other semiconductor devices while directly accessing design rules and a library of design features by interfacing with a GUI upon which the design layout is displayed. The design rules may be directly linked to the design features of the pattern library and imported into the device layout. The design rules may be directly accessed while designing the layout or while conducting a design rule check and the design features from the pattern library may be used in creating the layout.
摘要翻译：提供了一种用于设计集成电路或其他半导体器件的布局的系统和方法，同时通过与显示设计布局的GUI对接地直接访问设计规则和设计特征库。设计规则可以直接链接到图案库的设计特征并导入设备布局。设计规则可以在设计布局时进行直接访问，或者在进行设计规则检查时，可以使用图案库中的设计特征来创建布局。

7. 发明授权

US06169314A Layout pattern for improved MOS device matching 有权
标题翻译：改善MOS器件匹配的布局图案
公开(公告)号：US06169314A
公开(公告)日：2001-01-02
申请号：US09345358
申请日：1999-07-01
申请人： Shyh-Chyi Wong , Pin-Nan Tseng , Jyh-Kang Ting
发明人： Shyh-Chyi Wong , Pin-Nan Tseng , Jyh-Kang Ting
IPC分类号： H01L2976
CPC分类号： H01L27/0207 , H01L27/0203 , H01L27/088
摘要： This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.
摘要翻译：本发明提供了一种用于匹配精密模拟电路中匹配对中使用的金属氧化物半导体场效应晶体管对的电路布局图案和布局方法。该布局使用虚拟金属氧化物场效应晶体管或MOSFET，以在匹配的对中的每个MOSFET周围保持相同的环境。匹配对中的MOSFET处于单行，匹配对中的每个MOSFET都具有与其两侧相邻的虚设MOSFET。虚拟MOSFET可以是匹配对的一部分，可以用于电路的其他部分，也可以不使用。使用虚拟MOSFET可以使匹配对中每个MOSFET周围的环境保持一致，从而改善了匹配特性。

8. 发明授权

US5952698A Layout pattern for improved MOS device matching 失效
标题翻译：改善MOS器件匹配的布局图案
公开(公告)号：US5952698A
公开(公告)日：1999-09-14
申请号：US524537
申请日：1995-09-07
申请人： Shyh-Chyi Wong , Pin-Nan Tseng , Jyh-Kang Ting
发明人： Shyh-Chyi Wong , Pin-Nan Tseng , Jyh-Kang Ting
IPC分类号： H01L27/02 , H01L27/088 , H01L29/76 , H01L31/062
CPC分类号： H01L27/0207 , H01L27/0203 , H01L27/088
摘要： This invention provides a circuit layout pattern and layout method for matching pairs of metal oxide semiconductor field effect transistors used in matched pairs in precision analog circuits. The layout uses dummy Metal oxide field effect transistors, or MOSFETs, to keep the environment the same around each of the MOSFETs in a matched pair. The MOSFETs in a matched pair are in a single row with each MOSFET in the matched pair having dummy MOSFETs adjacent to it on either side. The dummy MOSFETs can be part of the matched pair, can be used in other parts of the circuit, or may not be used. The use of dummy MOSFETs keeps the environment around each MOSFET in the matched pair the same and this improves the matching characteristics.
摘要翻译：本发明提供了一种用于匹配精密模拟电路中匹配对中使用的金属氧化物半导体场效应晶体管对的电路布局图案和布局方法。该布局使用虚拟金属氧化物场效应晶体管或MOSFET，以在匹配的对中的每个MOSFET周围保持相同的环境。匹配对中的MOSFET处于单行，匹配对中的每个MOSFET都具有与其两侧相邻的虚设MOSFET。虚拟MOSFET可以是匹配对的一部分，可以用于电路的其他部分，也可以不使用。使用虚拟MOSFET可以使匹配对中每个MOSFET周围的环境保持一致，从而改善了匹配特性。

9. 发明授权

US5838032A Precision capacitor array 失效
标题翻译：精密电容阵列
公开(公告)号：US5838032A
公开(公告)日：1998-11-17
申请号：US801677
申请日：1997-02-18
申请人： Jyh-Kang Ting
发明人： Jyh-Kang Ting
IPC分类号： H01L27/08 , H01L27/10
CPC分类号： H01L27/0805 , Y10S257/92 , Y10S438/941
摘要： Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.
摘要翻译：作为模数转换器或数模转换器的一部分，电容器阵列可以并入硅集成电路中。单个电容器之间的电容比必须控制在1％以上。由于在蚀刻期间的微加载效应，沿着阵列边缘的电容器的电极的面积趋向于稍微小于完全位于阵列内部的电极的面积。本发明通过提供沿着阵列的周边设置的附加电极来解决这个问题，其间隔与阵列边缘相距离的距离与阵列内的电极之间的间隔隔开相同的距离。

10. 发明授权

US5635421A Method of making a precision capacitor array 失效
标题翻译：制作精密电容阵列的方法
公开(公告)号：US5635421A
公开(公告)日：1997-06-03
申请号：US490856
申请日：1995-06-15
申请人： Jyh-Kang Ting
发明人： Jyh-Kang Ting
IPC分类号： H01L27/08 , H01L21/8258
CPC分类号： H01L27/0805 , Y10S257/92 , Y10S438/941
摘要： Capacitor arrays may be incorporated within silicon integrated circuits as part of analog-to-digital or digital-to-analog converters. Capacitance ratios between individual capacitors need to be controlled to better than 1%. Because of microloading effects during etching, the areas of the electrodes of the capacitors located along the edges of the array have tended to be slightly less than the areas of electrodes located completely inside the array. The present invention solves this problem by providing additional electrodes located along the periphery of the array, spaced the same distance away from the array edge as the spacing between electrodes inside the array.
摘要翻译：作为模数转换器或数模转换器的一部分，电容器阵列可以并入硅集成电路中。单个电容器之间的电容比必须控制在1％以上。由于在蚀刻期间的微加载效应，沿着阵列边缘的电容器的电极的面积趋向于稍微小于完全位于阵列内部的电极的面积。本发明通过提供沿着阵列的周边设置的附加电极来解决这个问题，其间隔与阵列边缘相距离的距离与阵列内的电极之间的间隔隔开相同的距离。

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