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1. 发明授权

US08399292B2 Fabricating a semiconductor chip with backside optical vias 有权
标题翻译：制造具有背面光通孔的半导体芯片
公开(公告)号：US08399292B2
公开(公告)日：2013-03-19
申请号：US12827825
申请日：2010-06-30
申请人： Fuad Elias Doany , Christopher Vincent Jahnes , Clint Lee Schow , Mehmet Soyuer , Alexander V. Rylyakov
发明人： Fuad Elias Doany , Christopher Vincent Jahnes , Clint Lee Schow , Mehmet Soyuer , Alexander V. Rylyakov
IPC分类号： H01L21/768
CPC分类号： G02B6/12 , G02B6/4232 , G02B6/4246 , G02B6/4249 , G02B6/4259 , G02B6/4267 , H01L27/04 , H01L29/02 , H01L31/0203 , H01L2224/16225 , H01S5/40
摘要： Fabricating a semiconductor chip with backside optical vias is provided. A silicon wafer is received for processing. The silicon wafer includes an optically transparent oxide layer on a frontside of the silicon wafer. A complementary metal-oxide-semiconductor layer is formed on top of the optically transparent oxide layer. A backside of the silicon wafer is etched to form optical vias in a silicon substrate using the optically transparent oxide layer as an etch-stop.
摘要翻译：提供了具有背面光通孔的半导体芯片。接收硅晶片进行处理。硅晶片在硅晶片的前侧包括光学透明的氧化物层。在光学透明氧化物层的顶部上形成互补的金属氧化物半导体层。蚀刻硅晶片的背面以在硅衬底中形成光学通孔，使用光学透明氧化物层作为蚀刻停止层。

2. 发明授权

US08269291B2 Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters 失效
标题翻译：用于MEMS RF谐振器和滤波器的低温Bi-CMOS兼容工艺
公开(公告)号：US08269291B2
公开(公告)日：2012-09-18
申请号：US13007130
申请日：2011-01-14
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petraraca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petraraca , James Louis Speidell , James Francis Ziegler
IPC分类号： G01L9/00 , H01L29/84
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.
摘要翻译：一种微机电系统（MEMS）谐振器或滤波器，其包括第一导电层，在第一导电层中图案化的一个或多个电极，其用于信号输入，信号输出或DC偏置的功能，或这些功能的某些组合;抽真空腔，由下导电层和上结构层构成的谐振构件，在谐振构件和一个或多个电极之间的第一气隙，覆盖空腔的上膜，以及谐振构件和第二气隙之间的第二气隙上膜。

3. 发明授权

US06214482B1 Dielectric-layer for magneto-optic storage media structures 失效
标题翻译：用于磁光存储介质结构的介质层
公开(公告)号：US06214482B1
公开(公告)日：2001-04-10
申请号：US08224067
申请日：1994-04-07
申请人： Christopher Vincent Jahnes , Fletcher Jones , Joseph Skinner Logan , Michael Allen Russak
发明人： Christopher Vincent Jahnes , Fletcher Jones , Joseph Skinner Logan , Michael Allen Russak
IPC分类号： G11B566
CPC分类号： G11B11/10582 , Y10S428/90
摘要： A dielectric layer for use in a magneto-optic storage medium contains a compound glass of SiO2—MO2, SiO2—M2O3, or SiO2—M2O5 and combinations thereof where M is selected from Zr, Ti, Al, Nb, Y, Sn, In, Ta and Sb.
摘要翻译：用于磁光存储介质的电介质层包含SiO 2 -MO 2，SiO 2 -M 2 O 3或SiO 2 -M 2 O 5的复合玻璃及其组合，其中M选自Zr，Ti，Al，Nb，Y，Sn，In ，Ta和Sb。

4. 发明授权

US08263492B2 Through substrate vias 有权
标题翻译：通过衬底通孔
公开(公告)号：US08263492B2
公开(公告)日：2012-09-11
申请号：US12432243
申请日：2009-04-29
申请人： John Michael Cotte , Christopher Vincent Jahnes , Bucknell Chapman Webb
发明人： John Michael Cotte , Christopher Vincent Jahnes , Bucknell Chapman Webb
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.
摘要翻译：提出了用于形成通孔的方法和装置，例如，在包括衬底的半导体晶片的一部分中形成通孔的方法。该方法包括形成围绕基板的第一部分的沟槽，使得第一部分与基板的第二部分分离，在第一部分内形成穿过基板的孔，并在孔内形成第一金属。沟槽延伸穿过衬底。第一金属从基板的前表面延伸到基板的后表面。通孔包括孔和第一金属。

5. 发明授权

US08008095B2 Methods for fabricating contacts to pillar structures in integrated circuits 有权
标题翻译：在集成电路中制造与柱结构接触的方法
公开(公告)号：US08008095B2
公开(公告)日：2011-08-30
申请号：US11866455
申请日：2007-10-03
申请人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
发明人： Solomon Assefa , Gregory Costrini , Christopher Vincent Jahnes , Michael J. Rooks , Jonathan Zanhong Sun
IPC分类号： H01L21/00
CPC分类号： H01L43/12
摘要： A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.
摘要翻译：在集成电路中形成由垂直接触件接触的柱结构。硬掩模被形成并用于对柱结构的至少一部分进行图案化。硬掩模包含碳。随后，去除硬掩模。然后将导电材料沉积在先前由硬掩模占据的区域中以形成垂直接触。硬掩模可以例如包括类金刚石碳。柱结构可以具有小于约100纳米的宽度或直径。

6. 发明授权

US07943412B2 Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters 失效
标题翻译：用于MEMS RF谐振器和滤波器的低温Bi-CMOS兼容工艺
公开(公告)号：US07943412B2
公开(公告)日：2011-05-17
申请号：US10316254
申请日：2002-12-10
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
IPC分类号： H01L21/00
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process.
摘要翻译：一种形成微机电系统（MEMS）谐振器或滤波器的方法，其与在任何模拟，数字或混合信号集成电路（IC）工艺中的集成兼容，或者与这些工艺中的金属互连层的形成同时，由于其组成材料，加工步骤和制造温度。 MEMS谐振器或滤波器包含形成MEMS谐振器或滤波器的电极的较低金属电平，其可与IC上的现有金属互连电平中的任何一个或任何一个共享。它还包括谐振元件，该谐振元件由用于电连接和静电驱动的至少一个金属层和至少一个用于结构目的的电介质层组成。通过沉积并随后去除由碳基材料构成的牺牲层来产生电极和谐振构件之间的间隙。去除牺牲材料的方法是通过氧等离子体或在含氧环境中的退火。 MEMS谐振器或滤波器的真空封装方法是通过一个包含MEMS器件的空腔的装置提供的，其中填充有额外的牺牲材料并被密封。通过隔膜密封腔形成通孔; 如先前所述去除牺牲材料，并且在真空涂覆工艺中重新密封通孔。

7. 发明申请

US20100276786A1 Through Substrate Vias 有权
标题翻译：通过基板通风
公开(公告)号：US20100276786A1
公开(公告)日：2010-11-04
申请号：US12432243
申请日：2009-04-29
申请人： John Michael Cotte , Christopher Vincent Jahnes , Bucknell Chapman Webb
发明人： John Michael Cotte , Christopher Vincent Jahnes , Bucknell Chapman Webb
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： Methods and apparatus for forming through-vias are presented, for example, a method for forming a via in a portion of a semiconductor wafer comprising a substrate. The method comprises forming a trench surrounding a first part of the substrate such that the first part is separated from a second part of the substrate, forming a hole through the substrate within the first part, and forming a first metal within the hole. The trench extends through the substrate. The first metal extends from a front surface of the substrate to a back surface of the substrate. The via comprises the hole and the first metal.
摘要翻译：提出了用于形成通孔的方法和装置，例如，在包括衬底的半导体晶片的一部分中形成通孔的方法。该方法包括形成围绕基板的第一部分的沟槽，使得第一部分与基板的第二部分分离，在第一部分内形成穿过基板的孔，并在孔内形成第一金属。沟槽延伸穿过衬底。第一金属从基板的前表面延伸到基板的后表面。通孔包括孔和第一金属。

8. 发明授权

US07192868B2 Method of obtaining release-standing micro structures and devices by selective etch removal of protective and sacrificial layer using the same 失效
标题翻译：通过使用其去除保护层和牺牲层的方法来获得释放稳定的微结构和器件
公开(公告)号：US07192868B2
公开(公告)日：2007-03-20
申请号：US11053610
申请日：2005-02-08
申请人： John Michael Cotte , Nils Deneke Hoivik , Christopher Vincent Jahnes
发明人： John Michael Cotte , Nils Deneke Hoivik , Christopher Vincent Jahnes
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： B81C1/00476 , B81B2203/0118 , B81C2201/0132 , G01N1/32 , Y10S438/933
摘要： A method of patterning and releasing chemically sensitive low k films without the complication of a permanent hardmask stack, yielding an unaltered free-standing structure is provided. The method includes providing a structure including a Si-containing substrate having in-laid etch stop layers located therein; forming a chemically sensitive low k film and a protective hardmask having a pattern atop the structure; transferring the pattern to the chemically sensitive low k film to provide an opening that exposes a portion of the Si-containing substrate; and etching the exposed portion of the Si-containing substrate through the opening to provide a cavity in the Si-containing substrate in which a free-standing low k film structure is formed, while removing the hardmask. In accordance with the present invention, the etching comprises a XeF2 etch gas.
摘要翻译：提供了图案化和释放化学敏感性低k膜的方法，而不需要永久性硬掩模堆叠的复杂性，产生未改变的独立结构。该方法包括提供包括其中位于其中的内置蚀刻停止层的含Si衬底的结构; 形成化学敏感的低k膜和在结构顶部具有图案的保护性硬掩模; 将图案转移到化学敏感的低k膜上以提供暴露一部分含Si衬底的开口; 并且通过所述开口蚀刻含Si衬底的暴露部分，以在去除硬掩模的同时在其中形成独立的低k膜结构的含Si衬底中提供空腔。根据本发明，蚀刻包括XeF 2 N 2蚀刻气体。

9. 发明授权

US06953984B2 Hydrogenated oxidized silicon carbon material 有权
标题翻译：氢化氧化硅碳材料
公开(公告)号：US06953984B2
公开(公告)日：2005-10-11
申请号：US10827065
申请日：2004-04-19
申请人： Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Laurent Claude Perraud
发明人： Alfred Grill , Christopher Vincent Jahnes , Vishnubhai Vitthalbhai Patel , Laurent Claude Perraud
IPC分类号： H01L21/312 , H01L21/316 , H01L21/768 , H01L23/522 , H01L23/532 , H01L23/58 , H01L23/48
CPC分类号： H01L21/02167 , H01L21/02126 , H01L21/02211 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/02362 , H01L21/3122 , H01L21/31633 , H01L21/76828 , H01L21/76832 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.
摘要翻译：公开了可用作IC芯片中的互连电介质的低介电常数，热稳定的氢化氧化硅碳膜。还公开了利用等离子体增强化学气相沉积技术制造热稳定的氢化氧化硅碳低介电常数膜的方法。还公开了通过该方法制备的包含热稳定的氢化氧化硅碳低介电常数材料的绝缘层的电子器件。为了制造热稳定的氢化氧化硅碳低介电常数膜，优选具有环结构的特定的前体材料。

10. 发明授权

US06815329B2 Multilayer interconnect structure containing air gaps and method for making 有权
标题翻译：包含气隙的多层互连结构和制造方法
公开(公告)号：US06815329B2
公开(公告)日：2004-11-09
申请号：US10117797
申请日：2002-04-02
申请人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
发明人： Katherina E. Babich , Roy Arthur Carruthers , Timothy Joseph Dalton , Alfred Grill , Jeffrey Curtis Hedrick , Christopher Vincent Jahnes , Ebony Lynn Mays , Laurent Perraud , Sampath Purushothaman , Katherine Lynn Saenger
IPC分类号： H01L214763
CPC分类号： H01L21/76831 , H01L21/7681 , H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.
摘要翻译：描述了一种新颖的含气隙的互连布线结构，其在通孔级中结合有固体低k电介质，并且在布线层中结合了复合固体和气隙电介质。还提供了形成这种互连结构的方法。该方法很容易扩展到包含多个布线级别的互连结构，并且与双镶嵌后端（BEOL）处理兼容。

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