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1. 发明授权

US08269291B2 Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters 失效
标题翻译：用于MEMS RF谐振器和滤波器的低温Bi-CMOS兼容工艺
公开(公告)号：US08269291B2
公开(公告)日：2012-09-18
申请号：US13007130
申请日：2011-01-14
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petraraca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petraraca , James Louis Speidell , James Francis Ziegler
IPC分类号： G01L9/00 , H01L29/84
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.
摘要翻译：一种微机电系统（MEMS）谐振器或滤波器，其包括第一导电层，在第一导电层中图案化的一个或多个电极，其用于信号输入，信号输出或DC偏置的功能，或这些功能的某些组合;抽真空腔，由下导电层和上结构层构成的谐振构件，在谐振构件和一个或多个电极之间的第一气隙，覆盖空腔的上膜，以及谐振构件和第二气隙之间的第二气隙上膜。

2. 发明授权

US07943412B2 Low temperature Bi-CMOS compatible process for MEMS RF resonators and filters 失效
标题翻译：用于MEMS RF谐振器和滤波器的低温Bi-CMOS兼容工艺
公开(公告)号：US07943412B2
公开(公告)日：2011-05-17
申请号：US10316254
申请日：2002-12-10
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
IPC分类号： H01L21/00
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process.
摘要翻译：一种形成微机电系统（MEMS）谐振器或滤波器的方法，其与在任何模拟，数字或混合信号集成电路（IC）工艺中的集成兼容，或者与这些工艺中的金属互连层的形成同时，由于其组成材料，加工步骤和制造温度。 MEMS谐振器或滤波器包含形成MEMS谐振器或滤波器的电极的较低金属电平，其可与IC上的现有金属互连电平中的任何一个或任何一个共享。它还包括谐振元件，该谐振元件由用于电连接和静电驱动的至少一个金属层和至少一个用于结构目的的电介质层组成。通过沉积并随后去除由碳基材料构成的牺牲层来产生电极和谐振构件之间的间隙。去除牺牲材料的方法是通过氧等离子体或在含氧环境中的退火。 MEMS谐振器或滤波器的真空封装方法是通过一个包含MEMS器件的空腔的装置提供的，其中填充有额外的牺牲材料并被密封。通过隔膜密封腔形成通孔; 如先前所述去除牺牲材料，并且在真空涂覆工艺中重新密封通孔。

3. 发明申请

US20110109405A1 Low Temperature BI-CMOS Compatible Process For MEMS RF Resonators and Filters 失效
标题翻译：用于MEMS射频谐振器和滤波器的低温BI-CMOS兼容工艺
公开(公告)号：US20110109405A1
公开(公告)日：2011-05-12
申请号：US13007130
申请日：2011-01-14
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
IPC分类号： H03H9/24
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.
摘要翻译：一种微机电系统（MEMS）谐振器或滤波器，其包括第一导电层，在第一导电层中图案化的一个或多个电极，其用于信号输入，信号输出或DC偏置的功能，或这些功能的某些组合;抽真空腔，由下导电层和上结构层构成的谐振构件，在谐振构件和一个或多个电极之间的第一气隙，覆盖空腔的上膜，以及谐振构件和第二气隙之间的第二气隙上膜。

4. 发明申请

US20090108381A1 Low temperature bi-CMOS compatible process for MEMS RF resonators and filters 失效
标题翻译：用于MEMS RF谐振器和滤波器的低温双CMOS兼容工艺
公开(公告)号：US20090108381A1
公开(公告)日：2009-04-30
申请号：US10316254
申请日：2002-12-10
申请人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
发明人： Leena Paivikki Buchwalter , Kevin Kok Chan , Timothy Joseph Dalton , Christopher Vincent Jahnes , Jennifer Louise Lund , Kevin Shawn Petrarca , James Louis Speidell , James Francis Ziegler
IPC分类号： H03H9/24 , H01L23/28 , H01L21/56
CPC分类号： B81C1/00246 , B81B2201/0271 , B81C1/0023 , B81C2203/0735 , H03H3/0072 , H03H9/2405
摘要： A method of formation of a microelectromechanical system (MEMS) resonator or filter which is compatible with integration with any analog, digital, or mixed-signal integrated circuit (IC) process, after or concurrently with the formation of the metal interconnect layers in those processes, by virtue of its materials of composition, processing steps, and temperature of fabrication is presented. The MEMS resonator or filter incorporates a lower metal level, which forms the electrodes of the MEMS resonator or filter, that may be shared with any or none of the existing metal interconnect levels on the IC. It further incorporates a resonating member that is comprised of at least one metal layer for electrical connection and electrostatic actuation, and at least one dielectric layer for structural purposes. The gap between the electrodes and the resonating member is created by the deposition and subsequent removal of a sacrificial layer comprised of a carbon-based material. The method of removal of the sacrificial material is by an oxygen plasma or an anneal in an oxygen containing ambient. A method of vacuum encapsulation of the MEMS resonator or filter is provided through means of a cavity containing the MEMS device, filled with additional sacrificial material, and sealed. Access vias are created through the membrane sealing the cavity; the sacrificial material is removed as stated previously, and the vias are re-sealed in a vacuum coating process.
摘要翻译：一种形成微机电系统（MEMS）谐振器或滤波器的方法，其与在任何模拟，数字或混合信号集成电路（IC）工艺中的集成兼容，或者与这些工艺中的金属互连层的形成同时，由于其组成材料，加工步骤和制造温度。 MEMS谐振器或滤波器包含形成MEMS谐振器或滤波器的电极的较低金属电平，其可与IC上的现有金属互连电平中的任何一个或任何一个共享。它还包括谐振元件，该谐振元件由用于电连接和静电驱动的至少一个金属层和至少一个用于结构目的的电介质层组成。通过沉积并随后去除由碳基材料构成的牺牲层来产生电极和谐振构件之间的间隙。去除牺牲材料的方法是通过氧等离子体或在含氧环境中的退火。 MEMS谐振器或滤波器的真空封装方法是通过一个包含MEMS器件的空腔的装置提供的，其中填充有额外的牺牲材料并被密封。通过隔膜密封腔形成通孔; 如先前所述去除牺牲材料，并且在真空涂覆工艺中重新密封通孔。

5. 发明授权

US06818843B2 Microswitch with a micro-electromechanical system 有权
标题翻译：具有微机电系统的微动开关
公开(公告)号：US06818843B2
公开(公告)日：2004-11-16
申请号：US10361418
申请日：2003-02-10
申请人： Michael Meixner , Leena Paivikki Buchwalter , Jennifer Louise Lund , Hariklia Deligianni
发明人： Michael Meixner , Leena Paivikki Buchwalter , Jennifer Louise Lund , Hariklia Deligianni
IPC分类号： H01H5700
CPC分类号： H01H59/0009 , Y10T307/826
摘要： Microswitch, comprising a base element (G) with a contact surface (KG) and an electrode (EG), and a switching element (S) with a contact surface (KS) and an electrode (ES) disposed opposite the electrode (EG) of the base element (G) at a distance (g). The switching element (S) is provided with a spring constant and is connected at least with a part of its edge portion with the base element (G) in a fixed manner. The contact surfaces (KG, KS) form a switching contact which is closable against a reaction force caused by the spring constant by means of a voltage applied to the electrodes (EG, ES). The base element (G) and the switching element (S) each comprise an auxiliary electrode (HG, HS) at a distance (a) from the electrode (EG, ES), to which a voltage can be applied. For opening the switching contact the electrodes (EG, ES) have a first voltage potential (U1) and the auxiliary electrodes have a second voltage potential (U2) of the voltage. The voltage potentials (U1, U2) effect an accumulation of positive and negative charge carriers on the surface portions of the electrodes (EG, ES) and the auxiliary electrodes (HG, HS) such that surface portions with positive and negative charge carriers are opposite each other in a lateral direction and surface portions with the same charge carriers are opposite each other in an orthogonal direction.
摘要翻译：包括具有接触表面（KG）和电极（EG）的基体元件（G）和与电极（EG）相对设置的具有接触表面（KS）和电极（ES）的开关元件（S）的微动开关，（G）的距离（g）。开关元件（S）设置有弹簧常数，并且至少与其边缘部分的一部分与基座元件（G）固定连接。接触表面（KG，KS）形成开关触点，该开关触点通过施加到电极（EG，ES）的电压抵抗由弹簧常数引起的反作用力。基座元件（G）和开关元件（S）各自包括与电极（EG，ES）距离（a）的辅助电极（HG，HS），可施加电压。为了打开开关触点，电极（EG，ES）具有第一电压电位（U1），并且辅助电极具有电压的第二电压电位（U2）。电压电位（U1，U2）在电极（EG，ES）和辅助电极（HG，HS）的表面部分上影响正和负电荷载流子的积累，使得具有正和负电荷载体的表面部分相反在横向上彼此相对并且具有相同电荷载流子的表面部分在正交方向上彼此相对。

6. 发明授权

US07452568B2 Centrifugal method for filing high aspect ratio blind micro vias with powdered materials for circuit formation 有权
标题翻译：离心方法，用于提供具有电路形成的粉末材料的高纵横比盲孔
公开(公告)号：US07452568B2
公开(公告)日：2008-11-18
申请号：US11049846
申请日：2005-02-04
申请人： Gareth Hougham , Leena Paivikki Buchwalter , Stephen L. Buchwalter , Jon Casey , Claudius Feger , Matteo Flotta , Jeffrey D. Gelorme , Kathleen C. Hinge , Anurag Jain , Sung K. Kang , John U. Knickerbocker
发明人： Gareth Hougham , Leena Paivikki Buchwalter , Stephen L. Buchwalter , Jon Casey , Claudius Feger , Matteo Flotta , Jeffrey D. Gelorme , Kathleen C. Hinge , Anurag Jain , Sung K. Kang , John U. Knickerbocker
IPC分类号： B05D3/12 , B05D1/42
CPC分类号： H05K3/4053 , B05D1/002 , H01L21/486 , H01L21/76898 , H05K2201/09509 , H05K2203/1554
摘要： The present disclosure relates generally to semiconductor, integrated circuits, and particularly, but not by way of limitation, to centrifugal methods of filling high-aspect ratio vias and trenches with powders, pastes, suspensions of materials to act as any of a conducting, structural support, or protective member of an electronic component.
摘要翻译：本公开总体上涉及半导体，集成电路，特别是但不限于，用于填充高纵横比通孔和沟槽的离心方法，其具有粉末，浆料，材料的悬浮液，以充当导电的结构支撑或电子部件的保护构件。

7. 发明授权

US07615405B2 Method for precision assembly of integrated circuit chip packages 失效
标题翻译：集成电路芯片封装的精密组装方法
公开(公告)号：US07615405B2
公开(公告)日：2009-11-10
申请号：US11872331
申请日：2007-10-15
申请人： Paul Stephen Andry , Leena Paivikki Buchwalter , Raymond R. Horton , John Ulrich Knickerbocker , Cornelia K. Tsang , Steven Lorenz Wright
发明人： Paul Stephen Andry , Leena Paivikki Buchwalter , Raymond R. Horton , John Ulrich Knickerbocker , Cornelia K. Tsang , Steven Lorenz Wright
IPC分类号： H01L21/50 , H01L21/48 , H01L21/44
CPC分类号： H01L24/81 , H01L23/544 , H01L24/48 , H01L24/97 , H01L25/50 , H01L2223/54426 , H01L2223/54473 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/48227 , H01L2224/81001 , H01L2224/81054 , H01L2224/81136 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/85444 , H01L2224/85447 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/1517 , H01L2924/15174 , H01L2924/20109 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
摘要翻译：一种电子潜水及其制造方法。所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

8. 发明申请

US20080182362A1 METHOD FOR PRECISION ASSEMBLY OF INTEGRATED CIRCUIT CHIP PACKAGES 失效
标题翻译：集成电路芯片封装的精密组装方法
公开(公告)号：US20080182362A1
公开(公告)日：2008-07-31
申请号：US11872331
申请日：2007-10-15
申请人： Paul Stephen Andry , Leena Paivikki Buchwalter , Raymond R. Horton , John Ulrich Knickerbocker , Cornelia K. Tsang , Steven Lorenz Wright
发明人： Paul Stephen Andry , Leena Paivikki Buchwalter , Raymond R. Horton , John Ulrich Knickerbocker , Cornelia K. Tsang , Steven Lorenz Wright
IPC分类号： H01L21/00
CPC分类号： H01L24/81 , H01L23/544 , H01L24/48 , H01L24/97 , H01L25/50 , H01L2223/54426 , H01L2223/54473 , H01L2224/05568 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/13144 , H01L2224/13147 , H01L2224/16 , H01L2224/48227 , H01L2224/81001 , H01L2224/81054 , H01L2224/81136 , H01L2224/81203 , H01L2224/8121 , H01L2224/81815 , H01L2224/85444 , H01L2224/85447 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01018 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15157 , H01L2924/1517 , H01L2924/15174 , H01L2924/20109 , H01L2224/81 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An electronic dive and method of fabricating an electronic device. The method including placing a placement guide over a top surface of a module substrate, the placement guide having a guide opening, the guide opening extending from a top surface of the placement guide to a bottom surface of the placement guide; aligning the placement guide to an integrated circuit chip position on the module substrate; fixing the placement guide to the module substrate; placing an integrated circuit chip in the guide opening, sidewalls of the placement guide opening constraining electrically conductive bonding structures on bottom surface of the integrated circuit chip to self-align to an electrically conductive module substrate contact pad on the top surface of the module substrate in the integrated circuit chip position; and bonding the bonding structures to the module substrate contact pads, the bonding structures and the module substrate contact pads in direct physical and electrical contact after the bonding.
摘要翻译：一种电子潜水及其制造方法。所述方法包括将放置引导件放置在模块基板的顶表面上，所述放置引导件具有引导开口，所述引导开口从所述放置引导件的顶表面延伸到所述放置引导件的底表面; 将所述放置引导件对准所述模块基板上的集成电路芯片位置; 将所述放置引导件固定到所述模块基板; 将集成电路芯片放置在引导开口中，放置引导开口的侧壁约束集成电路芯片的底表面上的导电接合结构，以与模块基板的顶表面上的导电模块衬底接触焊盘自对准集成电路芯片位置; 以及在接合之后将结合结构粘合到模块衬底接触焊盘，接合结构和模块衬底接触焊盘，直接物理和电接触。

9. 发明申请

US20080157395A1 INTERCONNECTIONS FOR FLIP-CHIP USING LEAD-FREE SOLDERS AND HAVING IMPROVED REACTION BARRIER LAYERS 有权
标题翻译：使用无铅焊盘和改进的反应障碍层进行片芯互连
公开(公告)号：US20080157395A1
公开(公告)日：2008-07-03
申请号：US11616919
申请日：2006-12-28
申请人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valerie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
发明人： Luc Belanger , Stephen L. Buchwalter , Leena Paivikki Buchwalter , Ajay P. Giri , Jonathan H. Griffith , Donald W. Henderson , Sung Kwon Kang , Eric H. Laine , Christian Lavoie , Paul A. Lauro , Valerie Anne Oberson , Da-Yuan Shih , Kamalesh K. Srivastava , Michael J. Sullivan
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L24/12 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05599 , H01L2224/114 , H01L2224/11462 , H01L2224/1147 , H01L2224/116 , H01L2224/11849 , H01L2224/119 , H01L2224/13023 , H01L2224/13111 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/0104 , H01L2924/01041 , H01L2924/01042 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01057 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/30107 , H01L2924/01083 , H01L2924/01049 , H01L2224/13099
摘要： An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.
摘要翻译：一种适于将微电子器件芯片倒装连接到封装的互连结构，包括二层，三层或四层限流冶金，包括粘附/反应阻挡层，并且具有与含锡的组分反应的焊料可湿性层无铅焊料，使得可焊接层在焊接期间可以完全消耗，但在焊接期间与无铅焊料接触后，阻挡层保持不变。一个或多个无铅焊料球选择性地位于焊料润湿层上，该无铅焊球包含锡作为主要成分和一种或多种合金成分。

10. 发明授权

US07276787B2 Silicon chip carrier with conductive through-vias and method for fabricating same 有权
标题翻译：具有导电通孔的硅芯片载体及其制造方法
公开(公告)号：US07276787B2
公开(公告)日：2007-10-02
申请号：US10729254
申请日：2003-12-05
申请人： Daniel Charles Edelstein , Paul Stephen Andry , Leena Paivikki Buchwalter , Jon Alfred Casey , Sherif A. Goma , Raymond R. Horton , Gareth Geoffrey Hougham , Michael Wayne Lane , Xiao Hu Liu , Chirag Suryakant Patel , Edmund Juris Sprogis , Michelle Leigh Steen , Brian Richard Sundlof , Cornelia K. Tsang , George Frederick Walker
发明人： Daniel Charles Edelstein , Paul Stephen Andry , Leena Paivikki Buchwalter , Jon Alfred Casey , Sherif A. Goma , Raymond R. Horton , Gareth Geoffrey Hougham , Michael Wayne Lane , Xiao Hu Liu , Chirag Suryakant Patel , Edmund Juris Sprogis , Michelle Leigh Steen , Brian Richard Sundlof , Cornelia K. Tsang , George Frederick Walker
IPC分类号： H01L23/48 , H01L23/498 , H01L21/4763 , H01L29/40 , H01L23/52
CPC分类号： H01L23/49883 , H01L21/486 , H01L21/76898 , H01L23/49827 , H01L2224/16 , H01L2924/01004 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/3011 , H01L2924/3025 , H01L2924/00
摘要： A carrier structure and method for fabricating a carrier structure with through-vias each having a conductive structure with an effective coefficient of thermal expansion which is less than or closely matched to that of the substrate, and having an effective elastic modulus value which is less than or closely matches that of the substrate. The conductive structure may include concentric via fill areas having differing materials disposed concentrically therein, a core of the substrate material surrounded by an annular ring of conductive material, a core of CTE-matched non-conductive material surrounded by an annular ring of conductive material, a conductive via having an inner void with low CTE, or a full fill of a conductive composite material such as a metal-ceramic paste which has been sintered or fused.
摘要翻译：一种载体结构和方法，用于制造具有通孔的载流子结构，每个导通孔具有导电结构，其有效热膨胀系数小于或接近于基板的热膨胀系数，并且具有小于或等于或者与衬底的密切匹配。导电结构可以包括同心的通孔填充区域，其具有同心设置的不同材料，由导电材料的环形环包围的衬底材料的芯，由导电材料的环形环包围的CTE匹配的非导电材料的芯，具有低CTE的内部空隙的导电通孔，或已经烧结或熔合的诸如金属 - 陶瓷浆料的导电复合材料的完整填充物。

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