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    • 3. 发明授权
    • Method for exposing a semiconductor wafer by applying periodic movement to a component
    • 通过向组件施加周期性运动来暴露半导体晶片的方法
    • US07443484B2
    • 2008-10-28
    • US11128431
    • 2005-05-13
    • Christoph NölscherJoerg Tschischgale
    • Christoph NölscherJoerg Tschischgale
    • G03B27/52
    • G03B27/72G03F7/70258
    • A method of focus variation is described herein to achieve a one-step exposure of a wafer without the limitation of applying a complex y-tilt to a wafer stage. The position of the wafer surface to be exposed is periodically varied with respect to the focal plane, or vice versa. This relative movement between the focal plane, or best focus position along the optical axis and the wafer stage, or the wafer surface, is achieved by applying a movement to at least one of the reticle stage, one or more of the optical elements of the projection lens, and the wafer stage. The frequency of the movement is selected in dependence of the laser frequency (upper limit) or the scanning frequency (lower limit).
    • 本文描述了聚焦变化的方法以实现晶片的一步曝光,而不会对晶片台施加复杂的y倾斜。 要曝光的晶片表面的位置相对于焦平面周期性地变化,反之亦然。 通过将运动施加到标线片载物台中的至少一个,光学元件中的一个或多个光学元件或光学元件中的一个或多个来实现焦平面或沿着光轴和晶片台或晶片表面的最佳聚焦位置之间的这种相对移动 投影透镜和晶片台。 根据激光频率(上限)或扫描频率(下限)选择运动的频率。
    • 4. 发明授权
    • Method for forming a structure element on a wafer by means of a mask and a trimming mask assigned hereto
    • 通过掩模和分配给其的修整掩模在晶片上形成结构元件的方法
    • US07297468B2
    • 2007-11-20
    • US10743105
    • 2003-12-23
    • Christoph Nölscher
    • Christoph Nölscher
    • G03C5/58
    • G03F1/34G03F7/0035H01L21/0274
    • A method for forming a structure element in a layer arranged on a wafer by a trimming mask set, a developing step, and an etching step for the transfer of the structure pattern are carried out between the exposure steps carried out by the masks. Consequently, edges that are incipiently exposed below a limit value for the structure formation around the resist structures in a first resist layer, which are exposed using a first mask of the set, are transferred dimensionally accurately into an underlying layer on the wafer. Then, the exposure postprocesses the pattern of the first mask using a second mask of the set, the trimming mask, into a second, subsequently applied second resist layer.
    • 在由掩模执行的曝光步骤之间进行用于通过修整掩模组,显影步骤和用于传送结构图案的蚀刻步骤在晶片上形成的结构元件形成结构元件的方法。 因此,使用该组的第一掩模曝光的第一抗蚀剂层中的抗蚀剂结构周围的结构形成的限制值以下的边缘被精确地转移到晶片上的下层中。 然后,曝光后处理第一掩模的图案,使用该组的第二掩模(修剪掩模)进入第二随后施加的第二抗蚀剂层。
    • 5. 发明授权
    • Method for producing a structure on the surface of a substrate
    • 在基板表面上制造结构的方法
    • US08003538B2
    • 2011-08-23
    • US12114948
    • 2008-05-05
    • Christoph NölscherDietmar TemmlerPeter Moll
    • Christoph NölscherDietmar TemmlerPeter Moll
    • H01L21/302
    • H01L21/31144H01L21/0337H01L21/0338H01L21/3086H01L21/3088
    • The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.
    • 本发明涉及一种在基板表面上制造用作蚀刻掩模的结构的方法。 在这种情况下,第一种方法包括在衬底的表面上形成第一部分结构,其具有规则地排列并且基本相同地间隔开的结构元件。 第二种方法包括在衬底的表面上形成间隔物,其邻接第一部分结构的结构元件的侧壁,在间隔物之间​​提供切口。 第三种方法步骤包括将填充材料引入间隔件之间的切口中,间隔件的表面未被覆盖。 第四种方法步骤包括去除间隔物,以便形成具有填充材料的第二部分结构,并具有规则排列的结构元件并且基本相同地间隔开。 要制造的结构由第一部分结构和第二部分结构组成。
    • 6. 发明授权
    • Exposing a semiconductor wafer using two different spectral wavelengths and adjusting for chromatic aberration
    • 使用两种不同的光谱波长展现半导体晶片并调整色差
    • US07286207B2
    • 2007-10-23
    • US11116439
    • 2005-04-28
    • Christoph NölscherAndreas Jahnke
    • Christoph NölscherAndreas Jahnke
    • G03B27/68
    • G03F7/70575G03F7/70241G03F7/70333
    • A semiconductor wafer is exposed with a pattern from a mask or reticle in an exposure tool. The exposure tool has an adjustable lens system and a light source, which is tunable in wavelength. A first exposure is performed with a tuned first wavelength and a first setting of the lenses. Prior to performing a second exposure onto the same wafer and into the same resist layer, the wavelength of the light source is varied to a second wavelength in order to mimic a focus offset. A resulting image shift at the slit edges of the scanning system due to chromatic aberration is then corrected for by setting the lens system in dependence of the difference between the tuned first and second wavelength. Having tuned second wavelength of the light source and having set the lens system, the second exposure is performed. A continuous adjustment of the lens system based upon a continuously varying light source wavelength can be accomplished.
    • 半导体晶片在曝光工具中以掩模或掩模版的图案曝光。 曝光工具具有可调透镜系统和可调波长的光源。 第一曝光是通过调节的第一波长和透镜的第一设置来执行的。 在对相同的晶片和相同的抗蚀剂层进行第二次曝光之前,为了模拟聚焦偏移,光源的波长变化到第二波长。 然后通过根据调谐的第一和第二波长之间的差设置透镜系统来校正由于色差导致的扫描系统的狭缝边缘处的所得到的图像偏移。 调整光源的第二波长并设置透镜系统后,进行第二次曝光。 可以实现基于连续变化的光源波长的透镜系统的连续调节。
    • 7. 发明授权
    • Method for determining and removing phase conflicts on alternating phase masks
    • 用于确定和消除交替相位掩模上相位冲突的方法
    • US06730463B2
    • 2004-05-04
    • US10126371
    • 2002-04-19
    • Michael HeissmeierMarkus HofsässBurkhard LudwigMolela MoukaraChristoph Nölscher
    • Michael HeissmeierMarkus HofsässBurkhard LudwigMolela MoukaraChristoph Nölscher
    • G03C500
    • G03F1/30
    • A photoresist layer on a substrate wafer is exposed in first sections with a first exposure radiation and in second sections with a second exposure radiation that is phase-shifted by 180°. The first and second sections adjoin one another in boundary regions in which the photoresist layer is artificially not sufficiently exposed. Where a distance between these boundary regions is smaller than a photolithographically critical, least distance, the photoresist layer is exposed, at a first boundary region, with a third exposure radiation and at a second boundary region with a fourth exposure radiation phase-shifted by 180°. A trim mask provided for the process has a first translucent region and a second translucent region. The first light-transparent region and the second light-transparent region are fashioned such that the light passing through the first light-transparent region and the light passing through the second light-transparent region has a phase displacement of 180°.
    • 衬底晶片上的光致抗蚀剂层在具有第一曝光辐射的第一部分中暴露,并且在第二部分中具有相移180°的第二曝光辐射。 第一和第二部分在其中光致抗蚀剂层人为地不充分暴露的边界区域彼此相邻。 在这些边界区域之间的距离小于光刻临界的最小距离的情况下,光致抗蚀剂层在第一边界区域处以第三曝光辐射暴露,并且在第二边界区域处以第四曝光辐射相位偏移180° °。 为该工艺提供的修剪掩模具有第一半透明区域和第二半透明区域。 第一透光区域和第二透光区域被形成为使得穿过第一透光区域的光和穿过第二透光区域的光线具有180°的相位偏移。
    • 8. 发明授权
    • Method for producing a structure on the surface of a substrate
    • 在基板表面上制造结构的方法
    • US07368385B2
    • 2008-05-06
    • US11182066
    • 2005-07-15
    • Christoph NölscherDietmar TemmlerPeter Moll
    • Christoph NölscherDietmar TemmlerPeter Moll
    • H01L21/311
    • H01L21/31144H01L21/0337H01L21/0338H01L21/3086H01L21/3088
    • The present invention relates to a method for producing a structure serving as an etching mask on the surface of a substrate. In this case, a first method involves forming a first partial structure on the surface of the substrate, which has structure elements that are arranged regularly and are spaced apart essentially identically. A second method involves forming spacers on the surface of the substrate, which adjoin sidewalls of the structure elements of the first partial structure, cutouts being provided between the spacers. A third method step involves introducing filling material into the cutouts between the spacers, a surface of the spacers being uncovered. A fourth method step involves removing the spacers in order to form a second partial structure having the filling material and having structure elements that are arranged regularly and are spaced apart essentially identically. The structure to be produced is composed of the first partial structure and the second partial structure.
    • 本发明涉及一种在基板表面上制造用作蚀刻掩模的结构的方法。 在这种情况下,第一种方法包括在衬底的表面上形成第一部分结构,其具有规则地排列并且基本相同地间隔开的结构元件。 第二种方法包括在衬底的表面上形成间隔物,其邻接第一部分结构的结构元件的侧壁,在间隔物之间​​提供切口。 第三种方法步骤包括将填充材料引入间隔件之间的切口中,间隔件的表面未被覆盖。 第四种方法步骤包括去除间隔物,以便形成具有填充材料的第二部分结构,并具有规则排列的结构元件并且基本相同地间隔开。 要制造的结构由第一部分结构和第二部分结构组成。
    • 9. 发明授权
    • Phase shift mask
    • 相移掩模
    • US07361434B2
    • 2008-04-22
    • US10951805
    • 2004-09-29
    • Christoph Nölscher
    • Christoph Nölscher
    • G03F1/00
    • G03F1/34G03F1/32G03F1/36
    • Semitransparent and trenchlike, absorber-free structure elements are formed jointly on a photomask formed using phase mask technology. The trenchlike structure elements are formed as trench or mesa structure using CPL technology. In a layout, dense, but also if appropriate semi-isolated and isolated, but relatively thin pattern portions are selected to fabricate them on the photomask using CPL technology. By contrast, isolated, wider pattern portions are formed as semitransparent structure elements using halftone phase mask technology. The respective process windows are relatively large and are adapted to one another. The joint process window is enlarged. In the area of dynamic memory chips, structures in a memory cell array can be formed using CPL technology and the support regions using halftone phase mask technology. In logic circuits, thin conductor tracks using CPL technology and wider conductor tracks using halftone phase mask technology can be fabricated.
    • 半透明和沟槽状,无吸收体的结构元件在使用相位掩模技术形成的光掩模上共同形成。 沟槽状结构元件使用CPL技术形成为沟槽或台面结构。 在布局中,密集的,但是如果合适的话,则选择半隔离和隔离,但相对薄的图案部分,以使用CPL技术在光掩模上制造它们。 相比之下,使用半色调相位掩模技术,隔离,更宽的图案部分形成为半透明结构元件。 各个处理窗口相对较大并且彼此适配。 联合过程窗口被放大。 在动态存储器芯片领域,可以使用CPL技术和使用半色调相位掩模技术的支持区域来形成存储单元阵列中的结构。 在逻辑电路中,可以制造使用CPL技术的薄导体轨迹和使用半色调相位掩模技术的更宽的导体迹线。