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1. 发明申请

US20130217233A1 Methods for Controlling Line Dimensions in Spacer Alignment Double Patterning Semiconductor Processing 有权
标题翻译：用于控制间隔对齐中线路尺寸的方法双重图案化半导体处理
公开(公告)号：US20130217233A1
公开(公告)日：2013-08-22
申请号：US13402261
申请日：2012-02-22
申请人： Chia-Wei Chang , Ryan Chia-Jen Chen
发明人： Chia-Wei Chang , Ryan Chia-Jen Chen
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/76224 , H01L29/6681
摘要： Methods for forming uniformly spaced and uniformly shaped fine lines in semiconductor processes using double patterning. Dummy lines are formed over a substrate. Sidewall spacer material is deposited over the top and sides of each of the dummy lines. Etching is performed to remove the top surface sidewall spacer material from the tops of the dummy lines. The dummy material is removed by selective etching leaving the spacer material. A photolithographic mask is formed defining inner lines that are desired for a substrate etching step, and temporary lines outside of the desired lines. The temporary lines are partially masked. The temporary lines are partially removed while the inner desired lines are retained. A transfer etch process then patterns an underlying mask layer corresponding to the inner desired lines, and the mask layer is used for etching lines in an underlying semiconductor substrate.
摘要翻译：在半导体工艺中使用双重图案形成均匀间隔均匀形状的细线的方法。在衬底上形成虚线。侧壁间隔物材料沉积在每个虚拟线的顶部和侧面上。执行蚀刻以从虚线的顶部去除顶表面侧壁间隔物材料。通过选择性蚀刻离开间隔物材料去除虚拟材料。形成光刻掩模，限定用于基板蚀刻步骤所需的内线，并且在期望的线之外的临时线。临时线路被部分屏蔽。当保留内部所需的线时，部分地移除临时线。然后，转印刻蚀工艺对与内部期望线对应的底层掩模层进行图案化，并且掩模层用于蚀刻下面的半导体衬底中的线。

2. 发明授权

US08222441B2 Phosphorus-containing compounds and their preparing process and use 有权
标题翻译：含磷化合物及其制备方法和用途
公开(公告)号：US08222441B2
公开(公告)日：2012-07-17
申请号：US12385573
申请日：2009-04-13
申请人： Ching-Hsuan Lin , Tsung Li Lin , Chia Wei Chang , Kuen-Yuan Hwang , An-Pang Tu , Fang-Hsien Su
发明人： Ching-Hsuan Lin , Tsung Li Lin , Chia Wei Chang , Kuen-Yuan Hwang , An-Pang Tu , Fang-Hsien Su
IPC分类号： C07F9/32 , C08L71/02
CPC分类号： C07F9/657172 , C08K5/5313 , C09K21/12
摘要： A series of novel phosphorus-containing compounds having the following formula are disclosed: wherein R1-R12, A, B, D, X, and Y are as defined in the specification. A process for the preparation of the compound of formula (1), a curing agent, and a flame resistant epoxy resin and a preparation process thereof are also provided.
摘要翻译：公开了一系列具有下式的新型含磷化合物：其中R1-R12，A，B，D，X和Y如说明书中所定义。还提供了制备式（1）化合物，固化剂和阻燃环氧树脂的方法及其制备方法。

3. 发明申请

US20120062287A1 INJECTION-LOCKED FREQUENCY DIVIDING APPARATUS 失效
标题翻译：注射锁频分路器
公开(公告)号：US20120062287A1
公开(公告)日：2012-03-15
申请号：US13014692
申请日：2011-01-26
申请人： Sheng-Lyang Jang , Yu-Sheng Chen , Chia-Wei Chang , Cheng-Chen Liu
发明人： Sheng-Lyang Jang , Yu-Sheng Chen , Chia-Wei Chang , Cheng-Chen Liu
IPC分类号： H03L7/08
CPC分类号： H03B5/1212 , H03B5/1228 , H03B5/1243 , H03B19/14 , H03B2200/0034 , H03B2200/0074
摘要： An injection-locked frequency dividing apparatus including a frequency multiplier, a first linear mixer, a second linear mixer, and an oscillator is disclosed. The frequency multiplier receives a frequency signal and generates a multiple-frequency signal accordingly. The first and the second linear mixer both receive the multiple-frequency signal and respectively receive a first input signal and a second input signal, wherein the phases of the first and the second input signal are complementary. The first and the second linear mixer respectively mix the multiple-frequency signal with the first and the second input signal to respectively generate a first mixed signal and a second mixed signal. The oscillator generates the frequency signal. The oscillator further receives the first and the second mixed signal and generates a first output signal and a second output signal accordingly, wherein the phases of the first and the second output signal are complementary.
摘要翻译：公开了一种包括倍频器，第一线性混频器，第二线性混频器和振荡器的注入锁定分频装置。倍频器接收频率信号并相应地产生多频信号。第一和第二线性混频器都接收多频信号并分别接收第一输入信号和第二输入信号，其中第一和第二输入信号的相位是互补的。第一和第二线性混频器分别将多频信号与第一和第二输入信号混合，分别产生第一混合信号和第二混合信号。振荡器产生频率信号。振荡器还接收第一和第二混合信号，并相应地产生第一输出信号和第二输出信号，其中第一和第二输出信号的相位是互补的。

4. 发明申请

US20110285671A1 STYLUS AND ELECTRONIC DEVICE 审中-公开
标题翻译： STYLUS和电子设备
公开(公告)号：US20110285671A1
公开(公告)日：2011-11-24
申请号：US13082411
申请日：2011-04-08
申请人： Chia-Hsien Wu , Chia-Wei Chang , Wen-Chung Cheng
发明人： Chia-Hsien Wu , Chia-Wei Chang , Wen-Chung Cheng
IPC分类号： G06F3/033 , G09G5/00
CPC分类号： G06F3/0362 , G06F1/1626 , G06F3/03545 , G06F3/0487 , G06F2200/1632
摘要： This invention provides a stylus and an electronic device. The electronic device includes a stylus and a main body. The main body includes a display screen and at least one sensing element. The stylus is detachably connected with the main body. The stylus includes a penholder and a movable element. The movable element is disposed at the penholder and allowed to pivot around or slide along the penholder which is used as an axis. The sensing element senses the pivoting or sliding of the movable element to generate a control signal. The main body controls a display frame of the display screen according to the control signal.
摘要翻译：本发明提供了一种触针和电子装置。该电子设备包括触控笔和主体。主体包括显示屏和至少一个感测元件。触笔与主体可拆卸地连接。触笔包括一个笔杆和一个可动元件。可移动元件设置在笔杆上，并允许绕着或用作轴线的笔杆滑动。感测元件感测可移动元件的枢转或滑动以产生控制信号。主体根据控制信号控制显示画面的显示帧。

5. 发明申请

US20100260952A1 Furniture bow beam structure and manufacturing method thereof 审中-公开
标题翻译：家具弓梁结构及其制造方法
公开(公告)号：US20100260952A1
公开(公告)日：2010-10-14
申请号：US12588105
申请日：2009-10-05
申请人： Chia-Wei Chang
发明人： Chia-Wei Chang
IPC分类号： B32B1/00 , B27H1/00 , B27M3/00
CPC分类号： A47C7/40 , A47C5/043 , Y10T428/1348 , Y10T428/24628
摘要： A furniture bow beam structure and a manufacturing method thereof. By means of pressing, metal board materials are processed into different assembling members and connecting members. The assembling members and connecting members respectively have curvatures and configurations in conformity with different sections of the beam structure. Each assembling member has an opening that obliquely diverges to one side in width. The connecting member is connected to the opening and mated with the assembling member to form a hollow tubular support. Multiple supports are then connected with each other and rectified to form a complete beam structure with desired curvatures and shapes for connecting with other furniture components.
摘要翻译：家具弓形梁结构及其制造方法。通过压制，将金属板材料加工成不同的组装构件和连接构件。组装构件和连接构件分别具有与梁结构的不同部分一致的曲率和构造。每个组装构件具有以宽度向斜方向偏离一侧的开口。连接构件连接到开口并与组装构件配合以形成中空管状支撑件。然后，多个支撑件彼此连接并整流以形成具有期望的曲率和形状的完整的梁结构，用于与其他家具部件连接。

6. 发明授权

US07759239B1 Method of reducing a critical dimension of a semiconductor device 有权
标题翻译：降低半导体器件临界尺寸的方法
公开(公告)号：US07759239B1
公开(公告)日：2010-07-20
申请号：US12435552
申请日：2009-05-05
申请人： Yu Chao Lin , De-Fang Chen , Chia-Wei Chang , Yih-Ann Lin , Chao-Cheng Chen , Ryan Chia-Jen Chen , Weng Cheng
发明人： Yu Chao Lin , De-Fang Chen , Chia-Wei Chang , Yih-Ann Lin , Chao-Cheng Chen , Ryan Chia-Jen Chen , Weng Cheng
IPC分类号： H01L21/3205
CPC分类号： H01L21/76816 , H01L21/0337 , H01L21/31138 , H01L21/31144
摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.
摘要翻译：本公开提供了制造半导体器件的方法。该方法包括在衬底上形成栅极层，在栅极层上形成硬掩模层，在硬掩模层上形成第一材料层，形成在第一材料层上具有开口的图案化光刻胶层，蚀刻第一材料层，其包括在半导体器件上形成第二材料层并蚀刻第一和第二材料层，重复该循环，直到硬掩模层通过减小的开口暴露，在最后一个循环中形成的减小的开口，蚀刻硬掩模层以暴露栅极层，并且使用硬掩模层图案化栅极层。第一和第二材料层的蚀刻选择性小于第二材料层和光致抗蚀剂层的蚀刻选择性。

7. 发明授权

US07674986B2 Circuit board structure having capacitor array and embedded electronic component and method for fabricating the same 有权
标题翻译：具有电容器阵列和嵌入式电子部件的电路板结构及其制造方法
公开(公告)号：US07674986B2
公开(公告)日：2010-03-09
申请号：US11537417
申请日：2006-09-29
申请人： Chia-Wei Chang , Chung-Cheng Lien
发明人： Chia-Wei Chang , Chung-Cheng Lien
IPC分类号： H05K1/16
CPC分类号： H05K1/162 , H01L24/19 , H01L2224/04105 , H01L2924/14 , H05K1/185 , H05K3/4602 , H05K3/4626 , H05K2201/0209 , H05K2201/09536 , H05K2201/09672 , H05K2203/061 , H01L2924/00
摘要： A circuit board structure having a capacitor array and an embedded electronic component and a method for fabricating the same are proposed. Two carrier boards and a high dielectric constant material layer are provided, wherein the carrier boards have electronic components embedded therein and one surface of each carrier board has a plurality of electrode plates. The two carrier boards are laminated with the dielectric constant material layer interposed between them. The electrode plates on the surfaces of the carrier boards are opposite to each other across the high dielectric constant material layer to constitute a capacitor array. Therefore, the capacitor assembly for design of electronic devices is provided.
摘要翻译：提出了具有电容器阵列和嵌入式电子部件的电路板结构及其制造方法。提供了两个载体板和高介电常数材料层，其中载体板上嵌有电子部件，并且每个载体板的一个表面具有多个电极板。将两个载板叠置在介于它们之间的介电常数材料层。载体板表面上的电极板跨越高介电常数材料层彼此相对，以构成电容器阵列。因此，提供了用于设计电子设备的电容器组件。

8. 发明申请

US20090182116A1 MANUFACTURE OF PHOSPHORUS-CONTAINING DIAMINES AND THEIR DERIVATIVES 审中-公开
标题翻译：含磷含量及其衍生物的制备
公开(公告)号：US20090182116A1
公开(公告)日：2009-07-16
申请号：US12353460
申请日：2009-01-14
申请人： Ching-Hsuan LIN , Chia Wei CHANG , Tsung Li LIN
发明人： Ching-Hsuan LIN , Chia Wei CHANG , Tsung Li LIN
IPC分类号： C08G69/42 , C07F9/28
CPC分类号： C07F9/657172 , C07F9/5031 , C07F9/572 , C07F9/65505 , C08G69/42 , C08G73/1039 , C08G73/1046 , C08G73/1053 , C08G73/1085 , C08L79/08
摘要： A series of novel phosphorus-containing compounds having the following formula are disclosed: wherein Q, R5, Ar1, Ar2, A, and B are as defined in the specification. The present invention provides a process for the preparation of the compound of formula (I). The present invention also provides a compound of formula (PA) and a process for preparing the same. The present invention further provides a compound of formula (PI) and a process for preparing the same.
摘要翻译：公开了一系列具有下式的新型含磷化合物：其中Q，R5，Ar1，Ar2，A和B如说明书中所定义。本发明提供了制备式（I）化合物的方法。本发明还提供式（PA）的化合物及其制备方法。本发明还提供式（PI）化合物及其制备方法。

9. 发明申请

US20090091903A1 Stack structure of circuit boards embedded with semiconductor chips 有权
标题翻译：嵌入半导体芯片的电路板的堆叠结构
公开(公告)号：US20090091903A1
公开(公告)日：2009-04-09
申请号：US11588914
申请日：2006-10-27
申请人： Shih Ping Hsu , Chung Cheng Lien , Chia Wei Chang
发明人： Shih Ping Hsu , Chung Cheng Lien , Chia Wei Chang
IPC分类号： H05K1/18
CPC分类号： H05K1/185 , H01L23/5385 , H01L23/5389 , H01L2224/48227 , H01L2224/73265 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H05K3/4069 , H05K3/4614 , H05K3/462 , H05K2201/10378 , H05K2201/10674 , H05K2203/061 , H01L2224/48091 , H01L2924/00014 , H01L2924/00 , H01L2224/32145 , H01L2924/00015
摘要： A stack structure of circuit boards embedded with semiconductor chips is proposed. At least two circuit boards are provided. Each of the circuit boards includes circuit layers formed on surfaces thereof and at least one opening embedded with a semiconductor chip, wherein, the circuit layers have a plurality of conductive structures and electrically conductive pads, and the semiconductor chip has a plurality of electrode pads, and the conductive structures of the circuit layers are electrically conductive to the electrode pads of the semiconductor chip. At least one adhesive layer is formed between the two circuit boards and disposed with a conductive material corresponding in position to the electrically conductive pads of the circuit boards. Thus, a conductive path can be formed by the conductive material between the electrically conductive pads of the circuit boards, thereby establishing electrical connection between the two circuit boards.
摘要翻译：提出了嵌入半导体芯片的电路板的堆栈结构。提供至少两个电路板。每个电路板包括形成在其表面上的电路层和嵌入半导体芯片的至少一个开口，其中电路层具有多个导电结构和导电焊盘，并且半导体芯片具有多个电极焊盘，并且电路层的导电结构与半导体芯片的电极焊盘导电。在两个电路板之间形成至少一个粘合剂层，并且设置有与电路板的导电焊盘相对应的导电材料。因此，可以通过导电材料在电路板的导电焊盘之间形成导电路径，由此建立两个电路板之间的电连接。

10. 发明申请

US20090051341A1 BANDGAP REFERENCE CIRCUIT 审中-公开
标题翻译：带宽参考电路
公开(公告)号：US20090051341A1
公开(公告)日：2009-02-26
申请号：US12184528
申请日：2008-08-01
申请人： CHIA-WEI CHANG , UEI-SHAN UANG , YAN-HUA PENG
发明人： CHIA-WEI CHANG , UEI-SHAN UANG , YAN-HUA PENG
IPC分类号： G05F3/20
CPC分类号： G05F3/30
摘要： A bandgap reference circuit includes a PTAT current generating circuit for generating a PTAT current; a CTAT circuit generating circuit for generating a CTAT current; a node for receiving the PTAT current and the CTAT current; and, a first resistor connected between the node and a ground, wherein a reference voltage is derived from the first resistor when a superposed current of the PTAT current and the CTAT current is flowing through the first resistor.
摘要翻译：带隙参考电路包括用于产生PTAT电流的PTAT电流产生电路; 用于产生CTAT电流的CTAT电路产生电路; 用于接收PTAT电流和CTAT电流的节点; 以及连接在节点和地之间的第一电阻器，其中当PTAT电流和CTAT电流的叠加电流流过第一电阻器时，从第一电阻器导出参考电压。

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