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1. 发明授权

US07746890B2 Interface device and inter-chip communication interface apparatus to control data transfer between chips 有权
标题翻译：接口设备和芯片间通信接口设备，用于控制芯片间的数据传输
公开(公告)号：US07746890B2
公开(公告)日：2010-06-29
申请号：US11970019
申请日：2008-01-07
申请人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
发明人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
IPC分类号： H04J3/00
CPC分类号： G06F13/4226 , Y02D10/14 , Y02D10/151
摘要： An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.
摘要翻译：接口设备将数据转换为分组并使分组的至少一部分反转以减少在先前分组中的相应位置处的位切换的数量。附加到分组的反向比特指示分组是否被反转。发送包括反向比特和根据反向比特状态反转的分组部分的传输分组，并且从接收到的分组中恢复数据，根据接收到的分组的状态再次反转部分被反转反向位。

2. 发明申请

US20050010706A1 Dynamic bus arbitration method and bus arbiter 有权
标题翻译：动态总线仲裁方法和总线仲裁器
公开(公告)号：US20050010706A1
公开(公告)日：2005-01-13
申请号：US10766410
申请日：2004-01-28
申请人： Cheon-Su Lee
发明人： Cheon-Su Lee
IPC分类号： G06F13/00 , G06F13/36 , G06F13/364
CPC分类号： G06F13/364
摘要： A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a variable bus occupancy rate. When an interrupt signal provided to the CPU is activated, a second rate for the CPU, which is a sum of the first rate for the CPU and the variable rate, and the first rates for the second and third master devices are applied to a bus arbiter. When the interrupt signal is inactivated, a third rate for the CPU, which is obtained by subtracting the variable rate from the first rate for the CPU, and the first rates for the second and third master devices are applied to the bus arbiter. A use priority of the system bus is controlled according to the rates applied to the bus arbiter.
摘要翻译：一种仲裁作为第一主设备的CPU共享的系统总线的方法以及第二和第三主设备包括存储每个主设备的第一总线占用率和可变总线占用率。当提供给CPU的中断信号被激活时，作为CPU的第一速率和可变速率的总和的CPU的第二速率以及第二和第三主设备的第一速率被应用于总线仲裁者。当中断信号失效时，通过从CPU的第一速率减去可变速率而获得的CPU的第三速率和第二和第三主设备的第一速率被应用于总线仲裁器。根据应用于总线仲裁器的速率来控制系统总线的使用优先级。

3. 发明授权

US08239708B2 System on chip (SoC) device verification system using memory interface 有权
标题翻译：使用内存接口的片上系统（SoC）设备验证系统
公开(公告)号：US08239708B2
公开(公告)日：2012-08-07
申请号：US12455207
申请日：2009-05-29
申请人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
发明人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
IPC分类号： G06F11/26
CPC分类号： G06F11/261
摘要： A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.
摘要翻译：芯片系统（SoC）设备验证系统包括：包括一个或多个IP的SoC设备模型和存储器控制器; 接收来自SoC设备模型的指令并验证包括在SoC设备模型中的一个或多个IP的操作的外部IP验证模型; 以及总线选择模型，响应于从所述SoC设备模型的存储器控制器接收的存储器控制信号，选择外部IP验证模型和外部设备之一。

4. 发明申请

US20100017656A1 System on chip (SOC) device verification system using memory interface 有权
标题翻译：片上系统（SOC）器件验证系统采用存储器接口
公开(公告)号：US20100017656A1
公开(公告)日：2010-01-21
申请号：US12455207
申请日：2009-05-29
申请人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
发明人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
IPC分类号： G06F11/273
CPC分类号： G06F11/261
摘要： A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.
摘要翻译：芯片系统（SoC）设备验证系统包括：包括一个或多个IP的SoC设备模型和存储器控制器; 接收来自SoC设备模型的指令并验证包括在SoC设备模型中的一个或多个IP的操作的外部IP验证模型; 以及总线选择模型，响应于从所述SoC设备模型的存储器控制器接收的存储器控制信号，选择外部IP验证模型和外部设备之一。

5. 发明申请

US20080215781A1 SYSTEM INCLUDING BUS MATRIX 审中-公开
标题翻译：系统包括总线矩阵
公开(公告)号：US20080215781A1
公开(公告)日：2008-09-04
申请号：US12025479
申请日：2008-02-04
申请人： Jae-Shin Lee , Cheon-Su Lee , Jin-Kwon Park
发明人： Jae-Shin Lee , Cheon-Su Lee , Jin-Kwon Park
IPC分类号： G06F13/18
CPC分类号： G06F13/4022
摘要： A system has a first chip using a first bus matrix, and a second chip including second and third bus matrixes connected to the first bus matrix. The second bus matrix is connected to a plurality of bus masters of the second chip and the third bus matrix is connected to a plurality of bus slaves of the second chip.
摘要翻译：系统具有使用第一总线矩阵的第一芯片，以及包括连接到第一总线矩阵的第二和第三总线矩阵的第二芯片。第二总线矩阵连接到第二芯片的多个总线主机，并且第三总线矩阵连接到第二芯片的多个总线从站。

6. 发明申请

US20080191331A1 System in package semiconductor device suitable for efficient power management and method of managing power of the same 有权
标题翻译：适用于高效电源管理的封装半导体器件系统及其管理电源的方法
公开(公告)号：US20080191331A1
公开(公告)日：2008-08-14
申请号：US11891908
申请日：2007-08-14
申请人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
发明人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
IPC分类号： H01L23/50 , G06F1/26 , G06F1/32
CPC分类号： G06F1/32 , H01L25/18 , H01L2224/05554 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014
摘要： Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit. Therefore, power can be efficiently managed since power that is supplied to the chips of the SIP semiconductor device is managed by the alive blocks or the local interfaces of the chips.
摘要翻译：提供适用于高效电源管理的系统级封装（SIP）半导体器件，以及管理SIP半导体器件的功率的方法。 SIP半导体器件包括包括第一和第二芯片的芯片。每个芯片包括活动块，本地接口和知识产权（IP）块。活体块连续供电，以连续地处于开状态。本地接口向/从其他芯片发送/接收数据。 IP块分别存储和处理数据。芯片的活动块通过第一信号线单元相互连接，用于发送唤醒或初始化芯片所需的信号。活动块分别响应于外部唤醒指令信号或通过第一信号线单元传输的信号来分别控制芯片的功率。因此，由于提供给SIP半导体器件的芯片的功率由芯片的活动块或本地接口进行管理，所以可以有效地管理功率。

7. 发明授权

US07096293B2 Dynamic bus arbitration method and bus arbiter 有权
标题翻译：动态总线仲裁方法和总线仲裁器
公开(公告)号：US07096293B2
公开(公告)日：2006-08-22
申请号：US10766410
申请日：2004-01-28
申请人： Cheon-Su Lee
发明人： Cheon-Su Lee
IPC分类号： G06F13/00 , G06F13/36 , G06F13/14
CPC分类号： G06F13/364
摘要： A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a variable bus occupancy rate. When an interrupt signal provided to the CPU is activated, a second rate for the CPU, which is a sum of the first rate for the CPU and the variable rate, and the first rates for the second and third master devices are applied to a bus arbiter. When the interrupt signal is inactivated, a third rate for the CPU, which is obtained by subtracting the variable rate from the first rate for the CPU, and the first rates for the second and third master devices are applied to the bus arbiter. A use priority of the system bus is controlled according to the rates applied to the bus arbiter.
摘要翻译：一种仲裁作为第一主设备的CPU共享的系统总线的方法以及第二和第三主设备包括存储每个主设备的第一总线占用率和可变总线占用率。当提供给CPU的中断信号被激活时，作为CPU的第一速率和可变速率的总和的CPU的第二速率以及第二和第三主设备的第一速率被应用于总线仲裁者。当中断信号失效时，通过从CPU的第一速率减去可变速率而获得的CPU的第三速率和第二和第三主设备的第一速率被应用于总线仲裁器。根据应用于总线仲裁器的速率来控制系统总线的使用优先级。

8. 发明授权

US07953992B2 System in package semiconductor device suitable for efficient power management and method of managing power of the same 有权
标题翻译：适用于高效电源管理的封装半导体器件系统及其管理电源的方法
公开(公告)号：US07953992B2
公开(公告)日：2011-05-31
申请号：US11891908
申请日：2007-08-14
申请人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
发明人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F13/00
CPC分类号： G06F1/32 , H01L25/18 , H01L2224/05554 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014
摘要： Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit. Therefore, power can be efficiently managed since power that is supplied to the chips of the SIP semiconductor device is managed by the alive blocks or the local interfaces of the chips.
摘要翻译：提供适用于高效电源管理的系统级封装（SIP）半导体器件，以及管理SIP半导体器件的功率的方法。 SIP半导体器件包括包括第一和第二芯片的芯片。每个芯片包括活动块，本地接口和知识产权（IP）块。活体块连续供电，以连续地处于开状态。本地接口向/从其他芯片发送/接收数据。 IP块分别存储和处理数据。芯片的活动块通过第一信号线单元相互连接，用于发送唤醒或初始化芯片所需的信号。活动块分别响应于外部唤醒指令信号或通过第一信号线单元传输的信号来分别控制芯片的功率。因此，由于提供给SIP半导体器件的芯片的功率由芯片的活动块或本地接口进行管理，所以可以有效地管理功率。

9. 发明申请

US20080212580A1 INTERFACE DEVICE AND INTER-CHIP COMMUNICATION INTERFACE APPARATUS 有权
标题翻译：接口设备和机架间通信接口设备
公开(公告)号：US20080212580A1
公开(公告)日：2008-09-04
申请号：US11970019
申请日：2008-01-07
申请人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
发明人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
IPC分类号： H04L12/56
CPC分类号： G06F13/4226 , Y02D10/14 , Y02D10/151
摘要： An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.
摘要翻译：接口设备将数据转换为分组并使分组的至少一部分反转以减少在先前分组中的相应位置处的位切换的数量。附加到分组的反向比特指示分组是否被反转。发送包括反向比特和根据反向比特状态反转的分组部分的传输分组，并且从接收到的分组中恢复数据，根据接收到的分组的状态再次反转部分被反转反向位。

10. 发明授权

US06742056B2 Semiconductor device and method for initializing interface card using serial EEPROM 失效
标题翻译：使用串行EEPROM初始化接口卡的半导体器件和方法
公开(公告)号：US06742056B2
公开(公告)日：2004-05-25
申请号：US10265860
申请日：2002-10-07
申请人： Cheon-su Lee , Young-sik Kim , Soon-jae Won
发明人： Cheon-su Lee , Young-sik Kim , Soon-jae Won
IPC分类号： G06F300
CPC分类号： G06F13/122 , G06F13/28
摘要： A semiconductor device for initializing an interface card using a serial EEPROM and an initializing method allow for more effective use of a serial EEPROM used to store the initialization information, while not consuming additional circuit surface area. The method comprises initializing a semiconductor device, wherein the semiconductor device stores initialization information in a serial electrically erasable and programmable read only memory (EEPROM) and includes a direct memory access (DMA), a serial EEPROM interface, and a register interface that are connected to a common system bus according to the initialization information, the method comprising (a) setting an operational channel to allow the DMA automatically initialize the semiconductor device in a state where the semiconductor device is reset; (b) reading the initialization information from the serial EEPROM in response to the operational channel set in the DMA after the reset state of the semiconductor device is cancelled; (c) initializing the semiconductor device by writing the initialization information read out from the serial EEPROM to the register interface; (d) generating an initialization completion signal for indicating that the initialization of the semiconductor device is completed, and (e) automatically setting the register interface and the DMA to be prepared for normal operations after the initialization of the semiconductor device is completed.
摘要翻译：用于使用串行EEPROM初始化接口卡的半导体器件和初始化方法允许更有效地使用用于存储初始化信息的串行EEPROM，同时不消耗额外的电路表面积。该方法包括初始化半导体器件，其中半导体器件将初始化信息存储在串行电可擦除和可编程只读存储器（EEPROM）中，并且包括直接存储器访问（DMA），串行EEPROM接口和连接的寄存器接口根据所述初始化信息到所述公共系统总线，所述方法包括（a）设置操作信道以允许所述DMA在所述半导体器件被复位的状态下自动初始化所述半导体器件; （b）在半导体器件的复位状态被取消之后响应于在DMA中设置的操作通道从串行EEPROM读取初始化信息; （c）通过将从串行EEPROM读出的初始化信息写入寄存器接口来初始化半导体器件; （d）产生用于指示半导体器件的初始化完成的初始化完成信号，以及（e）在完成半导体器件的初始化之后，自动设置准备用于正常操作的寄存器接口和DMA。

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