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    • 1. 发明授权
    • Semiconductor device and method for initializing interface card using serial EEPROM
    • 使用串行EEPROM初始化接口卡的半导体器件和方法
    • US06742056B2
    • 2004-05-25
    • US10265860
    • 2002-10-07
    • Cheon-su LeeYoung-sik KimSoon-jae Won
    • Cheon-su LeeYoung-sik KimSoon-jae Won
    • G06F300
    • G06F13/122G06F13/28
    • A semiconductor device for initializing an interface card using a serial EEPROM and an initializing method allow for more effective use of a serial EEPROM used to store the initialization information, while not consuming additional circuit surface area. The method comprises initializing a semiconductor device, wherein the semiconductor device stores initialization information in a serial electrically erasable and programmable read only memory (EEPROM) and includes a direct memory access (DMA), a serial EEPROM interface, and a register interface that are connected to a common system bus according to the initialization information, the method comprising (a) setting an operational channel to allow the DMA automatically initialize the semiconductor device in a state where the semiconductor device is reset; (b) reading the initialization information from the serial EEPROM in response to the operational channel set in the DMA after the reset state of the semiconductor device is cancelled; (c) initializing the semiconductor device by writing the initialization information read out from the serial EEPROM to the register interface; (d) generating an initialization completion signal for indicating that the initialization of the semiconductor device is completed, and (e) automatically setting the register interface and the DMA to be prepared for normal operations after the initialization of the semiconductor device is completed.
    • 用于使用串行EEPROM初始化接口卡的半导体器件和初始化方法允许更有效地使用用于存储初始化信息的串行EEPROM,同时不消耗额外的电路表面积。 该方法包括初始化半导体器件,其中半导体器件将初始化信息存储在串行电可擦除和可编程只读存储器(EEPROM)中,并且包括直接存储器访问(DMA),串行EEPROM接口和连接的寄存器接口 根据所述初始化信息到所述公共系统总线,所述方法包括(a)设置操作信道以允许所述DMA在所述半导体器件被复位的状态下自动初始化所​​述半导体器件; (b)在半导体器件的复位状态被取消之后响应于在DMA中设置的操作通道从串行EEPROM读取初始化信息; (c)通过将从串行EEPROM读出的初始化信息写入寄存器接口来初始化半导体器件; (d)产生用于指示半导体器件的初始化完成的初始化完成信号,以及(e)在完成半导体器件的初始化之后,自动设置准备用于正常操作的寄存器接口和DMA。
    • 2. 发明申请
    • Array substrate for liquid crystal display device and method of fabricating the same
    • 液晶显示装置用阵列基板及其制造方法
    • US20100163879A1
    • 2010-07-01
    • US12458787
    • 2009-07-22
    • Dae-sung JungYoung-sik Kim
    • Dae-sung JungYoung-sik Kim
    • H01L33/00
    • H01L29/78603G02F1/13454G02F1/136204H01L27/124
    • A method of fabricating a liquid crystal display device includes: a first step of attaching a polarizing plate to an outer surface of a liquid crystal panel; a second step of attaching a tape carrier package (TCP) to the liquid crystal panel; a third step of coating a resin onto a rear surface of the TCP and a connection portion of the liquid crystal panel and the TCP; a fourth step of inspecting the TCP and the liquid crystal display panel; a fifth step of inserting the liquid crystal panel into a transferring means; a sixth step of transferring the transferring means; a seventh step of extracting the liquid crystal panel from the transferring means; a eighth step of attaching the TCP to a printed circuit board (PCB); a ninth step of inspecting the PCB, the TCP and the liquid crystal panel; and a tenth step of assembling the liquid crystal panel and a backlight unit with a plurality of frames.
    • 一种制造液晶显示装置的方法包括:将偏光板附接到液晶面板的外表面的第一步骤; 将带状载体封装(TCP)附接到液晶面板的第二步骤; 将树脂涂布到TCP的后表面上的第三步骤以及液晶面板和TCP的连接部分; 检查TCP和液晶显示面板的第四步骤; 将液晶面板插入转印装置的第五步骤; 传送传送装置的第六步骤; 从传送装置中提取液晶面板的第七步骤; 将TCP连接到印刷电路板(PCB)的第八步骤; 检查PCB,TCP和液晶面板的第九步; 以及组装液晶面板和具有多个框架的背光单元的第十步骤。
    • 5. 发明授权
    • Modular multiplier apparatus with reduced critical path of arithmetic operation and method of reducing the critical path of arithmetic operation in arithmetic operation apparatus
    • 具有降低运算运算关键路径的模块化乘法器和降低算术运算装置运算运算关键路径的方法
    • US08458242B2
    • 2013-06-04
    • US12660382
    • 2010-02-25
    • Young-sik KimMi-jung NohKyoung-moon AhnSun-soo Shin
    • Young-sik KimMi-jung NohKyoung-moon AhnSun-soo Shin
    • G06F7/72
    • G06F7/728
    • Provided are a modular multiplier apparatus in which a value of a long path carry (LPC) is predicted to reduce a critical path of an arithmetic operation of Montgomery modular multiplication, and a method of reducing the critical path of the arithmetic operation. The modular multiplier apparatus for obtaining a quotient and a result of an arithmetic operation of modular multiplication by using a modulus and two arbitrary constants includes: a reduction unit for obtaining a short path carry (SPC) included when a result of a modular arithmetic operation is obtained at a current stage, by using a medium calculation result; a carry predictor for predicting a long path carry (LPC) included when the result of the modular arithmetic operation is obtained at the current stage, by using the medium calculation result; and an accumulator for accumulating the result of the modular arithmetic operation by using the SPC and the LPC, wherein the medium calculation result is obtained by adding a result of a modular arithmetic operation obtained at a previous stage and a partial product of the two constants obtained at the current stage.
    • 提供了一种模数乘法器装置,其中预测长路径进位(LPC)的值以减少蒙哥马利乘法运算的关键路径,以及减少算术运算的关键路径的方法。 用于通过使用模数和两个任意常数来获得商和乘法运算的结果的模乘法器包括:用于获得当模运算的结果为包括的短路径进位(SPC)的缩小单元是 通过使用中等计算结果在当前阶段获得; 通过使用介质计算结果,当在当前阶段获得模数运算的结果时,预测包含的长路径进位(LPC)的进位预测器; 以及用于通过使用SPC和LPC累积模数运算结果的累加器,其中,通过将前一阶段获得的模运算结果和获得的两个常数的部分乘积相加得到介质计算结果 在目前阶段。
    • 7. 发明申请
    • Apparatus and methods for autonomous testing of random number generators
    • 随机数发生器自主测试的装置和方法
    • US20090037787A1
    • 2009-02-05
    • US11978464
    • 2007-10-29
    • Ihor VasyltsovYoung-sik KimHambardzumyan Eduard
    • Ihor VasyltsovYoung-sik KimHambardzumyan Eduard
    • G06F11/263G06F7/58
    • G07C15/006
    • Apparatus for testing a random number generator includes a random number generating unit that generates and outputs random numbers, and a switching unit that receives the random numbers from the random number generating unit and selectively transmits the random numbers in response to a switching control signal. A test unit performs a basic test on the random numbers to determine whether the transmitted random numbers are within a statistical range, controls the generation of random numbers according to a result of the basic test, and outputs the switching control signal based on whether a test suite is finished. Methods include performing a basic test on generated random numbers to determine whether the random numbers are within a statistical range, controlling the generation of random numbers in response to a result of the basic test and whether the basic test is finished, determining upon completion of the basic test if a test suite is finished, and if the test suite is finished, outputting the random numbers as final random numbers.
    • 用于测试随机数发生器的装置包括产生并输出随机数的随机数生成单元,以及从随机数生成单元接收随机数并根据切换控制信号有选择地发送随机数的切换单元。 测试单元对随机数执行基本测试,以确定所发送的随机数是否在统计范围内,根据基本测试的结果控制随机数的产生,并且基于测试是否输出切换控制信号 套房完成 方法包括对生成的随机数执行基本测试,以确定随机数是否在统计范围内,响应于基本测试的结果控制随机数的产生以及基本测试是否完成, 如果测试套件完成,基本测试,如果测试套件完成,则输出随机数作为最终随机数。
    • 9. 发明申请
    • MONTGOMERY MULTIPLIER HAVING EFFICIENT HARDWARE STRUCTURE
    • 具有有效硬件结构的蒙特卡罗公司
    • US20110231467A1
    • 2011-09-22
    • US13052524
    • 2011-03-21
    • Kyoung-moon AHNYoung-sik KimJong-hoon ShinSun-soo ShinJi-su Kang
    • Kyoung-moon AHNYoung-sik KimJong-hoon ShinSun-soo ShinJi-su Kang
    • G06F7/487G06F7/485
    • G06F7/728
    • A radix-2k Montgomery multiplier including an input coefficient generation unit to receive a multiplier, a multiplicand, a modulus, a sum and a previous sum, to generate and to output a partial product and a multiple modulus by using at least one of the multiplier, the multiplicand, the modulus and the sum, and to divide and to output the received previous sum into units of k bits, an accumulator circuit to receive the partial product, the multiple modulus and k bits of the previous sum from the input coefficient generation unit, and to generate and to output a carry and a sum by summing the partial product, the multiple modulus and the previous sum, and a carry propagation adder (CPA) circuit to generate and to output an ultimate sum by using the carry and the sum.
    • 一个radix-2k蒙哥马利乘数器,其包括用于接收乘法器的输入系数产生单元,乘法器,模数,和和先前和,以通过使用乘法器中的至少一个来产生和输出部分乘积和多重模数 ,被乘数,模数和和,并且将接收的先前和除以并输出到k位的单位,用于接收部分乘积的累加器电路,来自输入系数生成的先前和的多个模数和k个比特 并且通过将部分乘积,多重模量和前一个和相加来产生和输出一个进位和一个和以及一个进位传播加法器(CPA)电路,以通过使用进位和运算来产生和输出最终和 和。
    • 10. 发明申请
    • Phase splitters
    • 相分离器
    • US20070247205A1
    • 2007-10-25
    • US11730303
    • 2007-03-30
    • Young-sik Kim
    • Young-sik Kim
    • H03K5/13
    • H03K5/15013H03K5/1515
    • A phase splitter that receives an external clock signal and that generates first and second internal clock signals having a phase difference of 180° between the first and second internal clock signals, the phase splitter including: a first buffer that buffers the external clock signal and outputs a first signal; an inverting unit that inverts the external clock signal and outputs a second signal; a second buffer that buffers the second signal and outputs a third signal; a first interpolating signal generator that inverts the external clock signal and outputs a fourth signal; and a second interpolating signal generator that inverts the second signal and outputs a fifth signal. The first signal and the fifth signal are interpolated to generate the first internal clock signal. The third signal and the fourth signal are interpolated to generate the second internal clock signal.
    • 一种分相器,其接收外部时钟信号,并且产生在第一和第二内部时钟信号之间具有180°的相位差的第一和第二内部时钟信号,所述分相器包括:缓冲外部时钟信号和输出的第一缓冲器 第一个信号; 反相单元,其反转所述外部时钟信号并输出​​第二信号; 缓冲第二信号并输出​​第三信号的第二缓冲器; 第一内插信号发生器,其反转所述外部时钟信号并输出​​第四信号; 以及第二内插信号发生器,其反转第二信号并输出​​第五信号。 内插第一信号和第五信号以产生第一内部时钟信号。 内插第三信号和第四信号以产生第二内部时钟信号。