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1. 发明授权

US07746890B2 Interface device and inter-chip communication interface apparatus to control data transfer between chips 有权
标题翻译：接口设备和芯片间通信接口设备，用于控制芯片间的数据传输
公开(公告)号：US07746890B2
公开(公告)日：2010-06-29
申请号：US11970019
申请日：2008-01-07
申请人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
发明人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
IPC分类号： H04J3/00
CPC分类号： G06F13/4226 , Y02D10/14 , Y02D10/151
摘要： An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.
摘要翻译：接口设备将数据转换为分组并使分组的至少一部分反转以减少在先前分组中的相应位置处的位切换的数量。附加到分组的反向比特指示分组是否被反转。发送包括反向比特和根据反向比特状态反转的分组部分的传输分组，并且从接收到的分组中恢复数据，根据接收到的分组的状态再次反转部分被反转反向位。

2. 发明申请

US20080212580A1 INTERFACE DEVICE AND INTER-CHIP COMMUNICATION INTERFACE APPARATUS 有权
标题翻译：接口设备和机架间通信接口设备
公开(公告)号：US20080212580A1
公开(公告)日：2008-09-04
申请号：US11970019
申请日：2008-01-07
申请人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
发明人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
IPC分类号： H04L12/56
CPC分类号： G06F13/4226 , Y02D10/14 , Y02D10/151
摘要： An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.
摘要翻译：接口设备将数据转换为分组并使分组的至少一部分反转以减少在先前分组中的相应位置处的位切换的数量。附加到分组的反向比特指示分组是否被反转。发送包括反向比特和根据反向比特状态反转的分组部分的传输分组，并且从接收到的分组中恢复数据，根据接收到的分组的状态再次反转部分被反转反向位。

3. 发明申请

US20080215781A1 SYSTEM INCLUDING BUS MATRIX 审中-公开
标题翻译：系统包括总线矩阵
公开(公告)号：US20080215781A1
公开(公告)日：2008-09-04
申请号：US12025479
申请日：2008-02-04
申请人： Jae-Shin Lee , Cheon-Su Lee , Jin-Kwon Park
发明人： Jae-Shin Lee , Cheon-Su Lee , Jin-Kwon Park
IPC分类号： G06F13/18
CPC分类号： G06F13/4022
摘要： A system has a first chip using a first bus matrix, and a second chip including second and third bus matrixes connected to the first bus matrix. The second bus matrix is connected to a plurality of bus masters of the second chip and the third bus matrix is connected to a plurality of bus slaves of the second chip.
摘要翻译：系统具有使用第一总线矩阵的第一芯片，以及包括连接到第一总线矩阵的第二和第三总线矩阵的第二芯片。第二总线矩阵连接到第二芯片的多个总线主机，并且第三总线矩阵连接到第二芯片的多个总线从站。

4. 发明授权

US06978322B2 Embedded controller for real-time backup of operation states of peripheral devices 失效
标题翻译：嵌入式控制器，用于实时备份外围设备的运行状态
公开(公告)号：US06978322B2
公开(公告)日：2005-12-20
申请号：US10446307
申请日：2003-05-28
申请人： Jin-Kwon Park
发明人： Jin-Kwon Park
IPC分类号： G06F13/28 , G06F3/00 , H02H3/05
CPC分类号： G06F11/1402
摘要： An embedded controller includes a central processing unit, a memory interface for interface with an external memory, and a function block or peripheral device with a register for storing operation state information. The peripheral device includes a detection circuit, a storage unit, for example in the form of a FIFO, a multiplexer, and a direct memory access (DMA) controller. The state detection circuit activates a flag signal whenever the operation state information of the register is varied, and the FIFO stores the operation state information from the register in response to the flag signal. The multiplexer is controlled by the DMA controller and transmits the operation state information of the FIFO to an internal bus. As a result, the operation state information of the FIFO is stored in the external memory through the memory interface.
摘要翻译：嵌入式控制器包括中央处理单元，用于与外部存储器接口的存储器接口，以及具有用于存储操作状态信息的寄存器的功能块或外围设备。外围设备包括检测电路，存储单元，例如以FIFO，多路复用器和直接存储器访问（DMA）控制器的形式。每当寄存器的操作状态信息改变时，状态检测电路就激活标志信号，并且FIFO响应于标志信号存储来自寄存器的操作状态信息。多路复用器由DMA控制器控制，并将FIFO的操作状态信息发送到内部总线。结果，FIFO的操作状态信息通过存储器接口存储在外部存储器中。

5. 发明申请

US20050160333A1 Embedded micro computer unit (MCU) for high-speed testing using a memory emulation module and a method of testing the same 有权
标题翻译：使用内存仿真模块进行高速测试的嵌入式微型计算机单元（MCU）及其测试方法
公开(公告)号：US20050160333A1
公开(公告)日：2005-07-21
申请号：US11013116
申请日：2004-12-15
申请人： Jin-Kwon Park
发明人： Jin-Kwon Park
IPC分类号： G06F11/22 , G01R31/28 , G06F11/00 , G06F11/26 , G11C29/00 , G11C29/48
CPC分类号： G11C29/48 , G06F11/261 , G11C2029/0401 , G11C2029/1806
摘要： Provided are an embedded micro computer unit (MCU) using a memory emulation module and a method of testing the embedded MCU. The embedded MCU includes an internal memory that is connected to bus master devices for storing temporary data of the bus master devices and a test vector in a test mode, a memory controller for accessing the internal memory or an external memory when a processor core is operated, and a memory emulation module that is connected between the memory controller and the internal memory for storing the test vector in the internal memory in the test mode.
摘要翻译：提供了使用存储器仿真模块的嵌入式微计算机单元（MCU）和测试嵌入式MCU的方法。嵌入式MCU包括连接到总线主设备的内部存储器，用于存储总线主设备的临时数据和测试模式中的测试向量，当处理器核心被操作时用于访问内部存储器或外部存储器的存储器控制器以及存储器仿真模块，其连接在存储器控制器和内部存储器之间，用于在测试模式中将测试向量存储在内部存储器中。

6. 发明授权

US07222282B2 Embedded micro computer unit (MCU) for high-speed testing using a memory emulation module and a method of testing the same 有权
标题翻译：使用内存仿真模块进行高速测试的嵌入式微型计算机单元（MCU）及其测试方法
公开(公告)号：US07222282B2
公开(公告)日：2007-05-22
申请号：US11013116
申请日：2004-12-15
申请人： Jin-Kwon Park
发明人： Jin-Kwon Park
IPC分类号： G06F11/00
CPC分类号： G11C29/48 , G06F11/261 , G11C2029/0401 , G11C2029/1806
摘要： Provided are an embedded micro computer unit (MCU) using a memory emulation module and a method of testing the embedded MCU. The embedded MCU includes an internal memory that is connected to bus master devices for storing temporary data of the bus master devices and a test vector in a test mode, a memory controller for accessing the internal memory or an external memory when a processor core is operated, and a memory emulation module that is connected between the memory controller and the internal memory for storing the test vector in the internal memory in the test mode.
摘要翻译：提供了使用存储器仿真模块的嵌入式微计算机单元（MCU）和测试嵌入式MCU的方法。嵌入式MCU包括连接到总线主设备的内部存储器，用于存储总线主设备的临时数据和测试模式中的测试向量，当处理器核心被操作时用于访问内部存储器或外部存储器的存储器控制器以及存储器仿真模块，其连接在存储器控制器和内部存储器之间，用于在测试模式中将测试向量存储在内部存储器中。

7. 发明申请

US20070143573A1 Data processing apparatus and method using translation table emulation 审中-公开
标题翻译：数据处理装置和方法使用翻译表仿真
公开(公告)号：US20070143573A1
公开(公告)日：2007-06-21
申请号：US11483450
申请日：2006-07-10
申请人： Jin-Kwon Park
发明人： Jin-Kwon Park
IPC分类号： G06F12/00
CPC分类号： G06F12/10
摘要： A data processing system comprising a central processing unit (CPU), a memory management unit (MMU), and a translation table emulation module (TTE). The CPU outputs a virtual address. The MMU generates a translation table address corresponding to the virtual address and transforms the virtual address into a physical address from a descriptor. The TTE receives the translation table address and generates the descriptor needed to map the virtual address to the physical address.
摘要翻译：一种数据处理系统，包括中央处理单元（CPU），存储器管理单元（MMU）和转换表仿真模块（TTE）。 CPU输出虚拟地址。 MMU生成与虚拟地址对应的转换表地址，并将虚拟地址从描述符转换为物理地址。 TTE接收转换表地址，并生成将虚拟地址映射到物理地址所需的描述符。

8. 发明授权

US07027308B2 Printed circuit board method and apparatus 失效
标题翻译：印刷电路板方法和装置
公开(公告)号：US07027308B2
公开(公告)日：2006-04-11
申请号：US10444989
申请日：2003-05-27
申请人： Jin-Kwon Park , Chan-youn Won
发明人： Jin-Kwon Park , Chan-youn Won
IPC分类号： H05K7/02 , H05K7/06 , H05K7/08 , H05K7/10
CPC分类号： H05K1/0246 , H01R12/721 , H01R13/658 , H05K1/0231 , H05K1/14 , H05K7/1429 , H05K2201/044 , H05K2201/10022 , H05K2201/10189 , H05K2201/1053
摘要： A PCB having a card slot receiving a card provided with signal input/output pins and a circuit element to provide extended capability is inserted, and having data transmission pins, a power pin and a ground pin in correspondence to the signal input/output pins, comprises an electronic device internally provided for impedance matching with the card, and having a first end connected to one of the data transmission pins and a second end connected to one of the power pin and the ground pin. With this configuration, a card slot internally comprises an electronic device for impedance matching, so that a space of the PCB can be efficiently utilized.
摘要翻译：插入具有接收设置有信号输入/输出引脚的卡的卡插槽和提供扩展能力的电路元件的PCB，并且具有对应于信号输入/输出引脚的数据传输引脚，电源引脚和接地引脚，包括内部提供用于与卡的阻抗匹配的电子设备，并且具有连接到数据传输引脚之一的第一端和连接到电源引脚和接地引脚之一的第二端。利用这种配置，卡槽内部包括用于阻抗匹配的电子设备，从而可以有效地利用PCB的空间。

9. 发明授权

US07729152B2 Pin configuration changing circuit, base chip and system in package including the same 失效
标题翻译：引脚配置更换电路，基片和系统在封装中包括相同
公开(公告)号：US07729152B2
公开(公告)日：2010-06-01
申请号：US12005258
申请日：2007-12-26
申请人： Jin-Kwon Park
发明人： Jin-Kwon Park
IPC分类号： G11C5/02
CPC分类号： G11C5/063 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB).
摘要翻译：基本芯片的引脚配置改变电路包括引脚配置改变寄存器（PCCR）和引脚配置改变逻辑单元（PCCLU）。当存储器改变时，PCCR存储并提供指示包括在连接到基本芯片的存储器中的多个引脚的第一连接顺序的引脚连接分配值。 PCCLU接收引脚连接分配值，并改变基片的多个内引脚的第二连接顺序。可以将各种存储器连接到基座芯片而无需额外的布线或印刷电路板（PCB）。

10. 发明申请

US20080212351A1 Pin configuration changing circuit, base chip and system in package including the same 失效
标题翻译：引脚配置更换电路，基片和系统在封装中包括相同
公开(公告)号：US20080212351A1
公开(公告)日：2008-09-04
申请号：US12005258
申请日：2007-12-26
申请人： Jin-Kwon Park
发明人： Jin-Kwon Park
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G11C5/063 , H01L25/18 , H01L2924/0002 , H01L2924/00
摘要： A pin configuration changing circuit of a base chip includes pin configuration changing register (PCCR) and a pin configuration changing logic unit (PCCLU). The PCCR stores and provides a pin connection assignment value indicating a first connection order of a plurality of pins included in a memory connected to the base chip, based on a type of the memory when the memory is changed. The PCCLU receives the pin connection assignment value and changes a second connection order of a plurality of inner pins of the base chip. Various memories can be connected to the base chip without extra wiring or a printed circuit board (PCB).
摘要翻译：基本芯片的引脚配置改变电路包括引脚配置改变寄存器（PCCR）和引脚配置改变逻辑单元（PCCLU）。当存储器改变时，PCCR存储并提供指示包括在连接到基本芯片的存储器中的多个引脚的第一连接顺序的引脚连接分配值。 PCCLU接收引脚连接分配值，并改变基片的多个内引脚的第二连接顺序。可以将各种存储器连接到基座芯片而无需额外的布线或印刷电路板（PCB）。

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