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1. 发明授权

US07953992B2 System in package semiconductor device suitable for efficient power management and method of managing power of the same 有权
标题翻译：适用于高效电源管理的封装半导体器件系统及其管理电源的方法
公开(公告)号：US07953992B2
公开(公告)日：2011-05-31
申请号：US11891908
申请日：2007-08-14
申请人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
发明人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F13/00
CPC分类号： G06F1/32 , H01L25/18 , H01L2224/05554 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014
摘要： Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit. Therefore, power can be efficiently managed since power that is supplied to the chips of the SIP semiconductor device is managed by the alive blocks or the local interfaces of the chips.
摘要翻译：提供适用于高效电源管理的系统级封装（SIP）半导体器件，以及管理SIP半导体器件的功率的方法。 SIP半导体器件包括包括第一和第二芯片的芯片。每个芯片包括活动块，本地接口和知识产权（IP）块。活体块连续供电，以连续地处于开状态。本地接口向/从其他芯片发送/接收数据。 IP块分别存储和处理数据。芯片的活动块通过第一信号线单元相互连接，用于发送唤醒或初始化芯片所需的信号。活动块分别响应于外部唤醒指令信号或通过第一信号线单元传输的信号来分别控制芯片的功率。因此，由于提供给SIP半导体器件的芯片的功率由芯片的活动块或本地接口进行管理，所以可以有效地管理功率。

2. 发明授权

US08239708B2 System on chip (SoC) device verification system using memory interface 有权
标题翻译：使用内存接口的片上系统（SoC）设备验证系统
公开(公告)号：US08239708B2
公开(公告)日：2012-08-07
申请号：US12455207
申请日：2009-05-29
申请人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
发明人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
IPC分类号： G06F11/26
CPC分类号： G06F11/261
摘要： A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.
摘要翻译：芯片系统（SoC）设备验证系统包括：包括一个或多个IP的SoC设备模型和存储器控制器; 接收来自SoC设备模型的指令并验证包括在SoC设备模型中的一个或多个IP的操作的外部IP验证模型; 以及总线选择模型，响应于从所述SoC设备模型的存储器控制器接收的存储器控制信号，选择外部IP验证模型和外部设备之一。

3. 发明申请

US20100017656A1 System on chip (SOC) device verification system using memory interface 有权
标题翻译：片上系统（SOC）器件验证系统采用存储器接口
公开(公告)号：US20100017656A1
公开(公告)日：2010-01-21
申请号：US12455207
申请日：2009-05-29
申请人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
发明人： Jin-kwon Park , Cheon-su Lee , Jae-shin Lee , Min-Joung Lee
IPC分类号： G06F11/273
CPC分类号： G06F11/261
摘要： A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.
摘要翻译：芯片系统（SoC）设备验证系统包括：包括一个或多个IP的SoC设备模型和存储器控制器; 接收来自SoC设备模型的指令并验证包括在SoC设备模型中的一个或多个IP的操作的外部IP验证模型; 以及总线选择模型，响应于从所述SoC设备模型的存储器控制器接收的存储器控制信号，选择外部IP验证模型和外部设备之一。

4. 发明申请

US20080191331A1 System in package semiconductor device suitable for efficient power management and method of managing power of the same 有权
标题翻译：适用于高效电源管理的封装半导体器件系统及其管理电源的方法
公开(公告)号：US20080191331A1
公开(公告)日：2008-08-14
申请号：US11891908
申请日：2007-08-14
申请人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
发明人： Cheon-su Lee , Jin-kwon Park , Jae-shin Lee
IPC分类号： H01L23/50 , G06F1/26 , G06F1/32
CPC分类号： G06F1/32 , H01L25/18 , H01L2224/05554 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014
摘要： Provided are a system in package (SIP) semiconductor device suitable for efficient power management, and a method of managing power of the SIP semiconductor device. The SIP semiconductor device includes chips including first and second chips. Each of the chips includes an alive block, a local interface, and an intellectual property (IP) block. The alive block is continuously supplied with power in order to continuously be in an on-state. The local interface transmits/receives data to/from other chips. The IP block individually stores and processes data. The alive blocks of the chips are connected to each other through a first signal line unit for transmitting a signal required to wake up or initialize the chips. The alive blocks control power to the chips, respectively, in response to an external wake-up instruction signal or the signal transmitted through the first signal line unit. Therefore, power can be efficiently managed since power that is supplied to the chips of the SIP semiconductor device is managed by the alive blocks or the local interfaces of the chips.
摘要翻译：提供适用于高效电源管理的系统级封装（SIP）半导体器件，以及管理SIP半导体器件的功率的方法。 SIP半导体器件包括包括第一和第二芯片的芯片。每个芯片包括活动块，本地接口和知识产权（IP）块。活体块连续供电，以连续地处于开状态。本地接口向/从其他芯片发送/接收数据。 IP块分别存储和处理数据。芯片的活动块通过第一信号线单元相互连接，用于发送唤醒或初始化芯片所需的信号。活动块分别响应于外部唤醒指令信号或通过第一信号线单元传输的信号来分别控制芯片的功率。因此，由于提供给SIP半导体器件的芯片的功率由芯片的活动块或本地接口进行管理，所以可以有效地管理功率。

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