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1. 发明申请

US20080212580A1 INTERFACE DEVICE AND INTER-CHIP COMMUNICATION INTERFACE APPARATUS 有权
标题翻译：接口设备和机架间通信接口设备
公开(公告)号：US20080212580A1
公开(公告)日：2008-09-04
申请号：US11970019
申请日：2008-01-07
申请人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
发明人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
IPC分类号： H04L12/56
CPC分类号： G06F13/4226 , Y02D10/14 , Y02D10/151
摘要： An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.
摘要翻译：接口设备将数据转换为分组并使分组的至少一部分反转以减少在先前分组中的相应位置处的位切换的数量。附加到分组的反向比特指示分组是否被反转。发送包括反向比特和根据反向比特状态反转的分组部分的传输分组，并且从接收到的分组中恢复数据，根据接收到的分组的状态再次反转部分被反转反向位。

2. 发明授权

US07746890B2 Interface device and inter-chip communication interface apparatus to control data transfer between chips 有权
标题翻译：接口设备和芯片间通信接口设备，用于控制芯片间的数据传输
公开(公告)号：US07746890B2
公开(公告)日：2010-06-29
申请号：US11970019
申请日：2008-01-07
申请人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
发明人： Jin-Kwon Park , Cheon-Su Lee , Jae-Shin Lee
IPC分类号： H04J3/00
CPC分类号： G06F13/4226 , Y02D10/14 , Y02D10/151
摘要： An interface device transforms data to a packet and inverts at least a portion of the packet to reduce a number of bit toggles at corresponding locations in a previous packet. A reverse bit appended to the packet indicates whether the packet is inverted. A transmission packet including the reverse bit and the portion of the packet inverted according to a state of the reverse bit is transmitted, and the data are recovered from a received packet, the portion of which that was inverted is inverted again according to the state of the reverse bit.
摘要翻译：接口设备将数据转换为分组并使分组的至少一部分反转以减少在先前分组中的相应位置处的位切换的数量。附加到分组的反向比特指示分组是否被反转。发送包括反向比特和根据反向比特状态反转的分组部分的传输分组，并且从接收到的分组中恢复数据，根据接收到的分组的状态再次反转部分被反转反向位。

3. 发明申请

US20080215781A1 SYSTEM INCLUDING BUS MATRIX 审中-公开
标题翻译：系统包括总线矩阵
公开(公告)号：US20080215781A1
公开(公告)日：2008-09-04
申请号：US12025479
申请日：2008-02-04
申请人： Jae-Shin Lee , Cheon-Su Lee , Jin-Kwon Park
发明人： Jae-Shin Lee , Cheon-Su Lee , Jin-Kwon Park
IPC分类号： G06F13/18
CPC分类号： G06F13/4022
摘要： A system has a first chip using a first bus matrix, and a second chip including second and third bus matrixes connected to the first bus matrix. The second bus matrix is connected to a plurality of bus masters of the second chip and the third bus matrix is connected to a plurality of bus slaves of the second chip.
摘要翻译：系统具有使用第一总线矩阵的第一芯片，以及包括连接到第一总线矩阵的第二和第三总线矩阵的第二芯片。第二总线矩阵连接到第二芯片的多个总线主机，并且第三总线矩阵连接到第二芯片的多个总线从站。

4. 发明申请

US20050010706A1 Dynamic bus arbitration method and bus arbiter 有权
标题翻译：动态总线仲裁方法和总线仲裁器
公开(公告)号：US20050010706A1
公开(公告)日：2005-01-13
申请号：US10766410
申请日：2004-01-28
申请人： Cheon-Su Lee
发明人： Cheon-Su Lee
IPC分类号： G06F13/00 , G06F13/36 , G06F13/364
CPC分类号： G06F13/364
摘要： A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a variable bus occupancy rate. When an interrupt signal provided to the CPU is activated, a second rate for the CPU, which is a sum of the first rate for the CPU and the variable rate, and the first rates for the second and third master devices are applied to a bus arbiter. When the interrupt signal is inactivated, a third rate for the CPU, which is obtained by subtracting the variable rate from the first rate for the CPU, and the first rates for the second and third master devices are applied to the bus arbiter. A use priority of the system bus is controlled according to the rates applied to the bus arbiter.
摘要翻译：一种仲裁作为第一主设备的CPU共享的系统总线的方法以及第二和第三主设备包括存储每个主设备的第一总线占用率和可变总线占用率。当提供给CPU的中断信号被激活时，作为CPU的第一速率和可变速率的总和的CPU的第二速率以及第二和第三主设备的第一速率被应用于总线仲裁者。当中断信号失效时，通过从CPU的第一速率减去可变速率而获得的CPU的第三速率和第二和第三主设备的第一速率被应用于总线仲裁器。根据应用于总线仲裁器的速率来控制系统总线的使用优先级。

5. 发明授权

US07096293B2 Dynamic bus arbitration method and bus arbiter 有权
标题翻译：动态总线仲裁方法和总线仲裁器
公开(公告)号：US07096293B2
公开(公告)日：2006-08-22
申请号：US10766410
申请日：2004-01-28
申请人： Cheon-Su Lee
发明人： Cheon-Su Lee
IPC分类号： G06F13/00 , G06F13/36 , G06F13/14
CPC分类号： G06F13/364
摘要： A method of arbitrating a system bus shared by a CPU, which is a first master device, and second and third master devices comprises storing a first bus occupancy rate for each master device and a variable bus occupancy rate. When an interrupt signal provided to the CPU is activated, a second rate for the CPU, which is a sum of the first rate for the CPU and the variable rate, and the first rates for the second and third master devices are applied to a bus arbiter. When the interrupt signal is inactivated, a third rate for the CPU, which is obtained by subtracting the variable rate from the first rate for the CPU, and the first rates for the second and third master devices are applied to the bus arbiter. A use priority of the system bus is controlled according to the rates applied to the bus arbiter.
摘要翻译：一种仲裁作为第一主设备的CPU共享的系统总线的方法以及第二和第三主设备包括存储每个主设备的第一总线占用率和可变总线占用率。当提供给CPU的中断信号被激活时，作为CPU的第一速率和可变速率的总和的CPU的第二速率以及第二和第三主设备的第一速率被应用于总线仲裁者。当中断信号失效时，通过从CPU的第一速率减去可变速率而获得的CPU的第三速率和第二和第三主设备的第一速率被应用于总线仲裁器。根据应用于总线仲裁器的速率来控制系统总线的使用优先级。

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